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参数资料
| 型号： | ADM1028ARQZ-REEL7 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封装： | MO-137AB, QSOP-16 |
| 文件页数： | 3/16页 |
| 文件大小： | 379K |
| 代理商： | ADM1028ARQZ-REEL7 |
REV. B
ADM1028
–11–
HARDWARE
TRIP POINT
THERM
ANALOG
OUTPUT
TEMP
PROGRAMMED
VALUE
FFh
5
PREVIOUS FAN
SPEED VALUE
Figure 8. Operation of
THERM Outputs
When the Fault Tolerant Fan Control state is exited, the analog
FAN_SPD output returns to its previously programmed value,
which may have been changed during the time that the FAN_SPD
output was forced to FFh.
INTERRUPT STRUCTURE
The Interrupt Structure of the ADM1028 is shown in more
detail in Figure 9. As each measurement value is obtained and
stored in the appropriate value register, the value and the limits
from the corresponding limit registers are fed to the high and
low limit comparators. The result of each comparison (1 = out
of limit, 0 = in limit) is routed to the corresponding bit input of
the Interrupt Status Register via a data demultiplexer, and used
to set that bit high or low as appropriate.
The Interrupt Mask Register has bits corresponding to each of
the Interrupt Status Register Bits. Setting an Interrupt Mask Bit
high forces the corresponding Status Bit output low, while set-
ting an Interrupt Mask Bit low allows the corresponding Status
Bit to be asserted. After masking, the status bits are all OR’d
together to produce the
INT output, which will pull low if any
unmasked status bit goes high, i.e. when any measured value
goes out of limit.
The
INT output is enabled when Bit 1 of the Configuration
Register (
INT_Enable) is high.
STATUS
BIT
MASK
BIT
MASK GATING
8
HIGH
LIMIT
VALUE
LOW
LIMIT
FROM
VALUE
AND LIMIT
REGISTERS
1 = OUT
OF
LIMIT
INT. TEMP
FLAG1
FLAG2
INT. THERM
GPI
EXT. TEMP
EXT. THERM
DIODE FAULT
0
1
2
3
4
5
6
7
MASKING
DATA
FROM BUS
EIGHT MASK BITS
(SAME BIT
ORDER AS
STATUS
REGISTER)
HIGH
AND
LOW
LIMIT
COMPARA-
TORS
INTERRUPT
MASK
REGISTER
INTERRUPT
STATUS
REGISTER
DATA
DEMULTI-
PLEXER
CONFIGURATION
REGISTER
INT_ENABLE
INT
Figure 9. Interrupt Register Structure
INTERRUPT MASKING
Any of the bits in the Interrupt Status Register can be masked out
by setting the corresponding mask bit in the Interrupt Mask Regis-
ter. That interrupt source will then no longer generate an interrupt.
However, the bits in the status register will be set as normal.
INTERRUPT CLEARING
The Interrupt Status Register reflects out-of-limit conditions.
The Status bits may be individually cleared by writing a “1” to
the appropriate status bits. Writing a “1” to Bits 1 and 2 causes
software interrupts to be generated. Bit 4 (GPI) of the Interrupt
Status Register reflects the current status of the GPI pin, and so
cannot be cleared by writing to this bit.
The
INT output is cleared with the INT_Enable bit, which is
Bit 1 of the Configuration Register, without affecting the contents
of the Interrupt (
INT) Status Registers.
THERM OUTPUTS
The
THERMA, THERMB signals are functionally identical.
These system over-temperature outputs will assert together when
an over-temperature is detected.
THERMA (Pin 11) is an open
drain digital output which has an integrated pull-up resistor to
VCC3AUX. THERMB is an open drain digital output, intended to
drive external circuitry operating at a different supply voltage level.
THERM OPERATING MODE
THERM only responds to the “hardware” temperature limits at
addresses 14h and 18h, not to the software programmed limits.
The function of these registers was described earlier with regard
to fault tolerant fan speed control.
THERM will go low if the hardware temperature limit is exceeded
for three consecutive measurements. It will remain low until the
temperature falls five degrees below the limit for three consecu-
tive measurements. While
THERM is low, the analog output will
go to FFh to boost a controlled fan to full speed and
FAN_OFF
will be negated.
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