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| 型号： | ADM1029ARQZ-R7 |
| 厂商： | ON Semiconductor |
| 文件页数： | 28/50页 |
| 文件大小： | 402K |
| 描述： | IC SENSOR 2TEMP/FAN CTRL 24QSOP |
| 产品变化通告： | QSOP 24ld Pkg (MSL) Change 17/Jun/2010 |
| 标准包装： | 1,000 |
| 功能： | 风扇控制，温度监控器 |
| 传感器类型： | 内部和外部 |
| 感应温度： | 0°C ~ 100°C，外部传感器 |
| 精确度： | ±1°C 本地，±3°C 远程 |
| 拓扑： | ADC，风扇控制，寄存器库 |
| 输出类型： | 开路漏极 |
| 输出警报： | 是 |
| 输出风扇： | 是 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | 0°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 带卷 (TR) |
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ADM1029
http://onsemi.com
28
General Purpose Logic Input/Outputs
The ADM1029 has six dual-function pins (see Pin
Function Descriptions section) that may be configured as
general-purpose Logic I/O pins by setting the appropriate
bit(s) of the GPIO Present/AIN Register (address 05h) or as
their alternate functions by clearing these bits.
When configured as GPIO pins, each GPIO pin has a
Behavior Register associated with it (Registers 28h to 2Eh)
that may be used to configure the operation of the pin.
The GPIO pins may be configured as inputs or outputs.
When used as inputs, they may be configured to:
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Be Active High or Active Low
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Set/Clear a Bit in the Behavior Register when GP Input
Is Asserted/Deasserted
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Latch a Bit In the Behavior Register when GP Input Is
Asserted (Must Be Cleared by Software)
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Assert CFAULT
when GP Input Asserted
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Assert INT
when GP Input Asserted
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Set Fan(s) to Alarm Speed when GP Input Asserted
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Set Fan(s) to Hot-plug Speed when GP Input Asserted
When Used as Outputs, They May Be Configured to:
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Be Active High or Low
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Be Asserted If a High Temperature Limit Is Exceeded
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Be Asserted If a Temperature Measurement Falls
Below a Low Limit
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Be Asserted If a Fan Fault Is Detected
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Be Asserted If a Fan Tach Limit Is Exceeded
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Be Asserted If an AIN High Limit Is Exceeded
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Be Asserted If an Analog Input Falls Below a Low
Limit
Figure 39 shows how to configure the GPIO pins to
handle different out-of-limit and fault events.
CFAULT
Output
The Cascade Fault output (CFAULT
), is an open-drain,
active low output, intended to communicate fault conditions
to other ADM1029s in a system, without the intervention of
the host processor. The other ADM1029s may then adjust
their fans speed to compensate, depending on the settings
of various registers.
CFAULT
is asserted if any of the following conditions
occurs:
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> A Hot-plug Event
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Setting Bit 5 of the Configuration Register (Address
01h) forces CFAULT
to be asserted
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> When a GPIO pin is configured as an input by setting
Bit 0 of the corresponding GPIO Behavior Register and
Bit 2 of the GPIO Behavior Register is also set,
CFAULT
will be asserted when the logic input is
asserted (high or low depending on the polarity bit,
Bit 1 of the corresponding GPIO Behavior Register)
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> If Bit 0 of a Temp. Fault Action Register is set
(40h Local Sensor, 41h Remote 1, 42h Remote 2),
CFAULT
will be asserted if the corresponding
temperature high limit is exceeded
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> If Bit 4 of a Temp. Fault Action Register is set,
CFAULT
will be asserted if a temperature input crosses
the corresponding temperature low limit, the direction
depending on the setting of Bit 3 of the Temp. Fault
Action Register. (0 = CFAULT
when input goes below
low limit, 1 = CFAULT
when input goes above low
limit)
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> If Bit 0 of a Fan Fault Action Register (18h or 19h) is
set, CFAULT
will be asserted when a tach measurement
for the corresponding fan exceeds the set limit
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> If Bit 0 of a Fan Fault Action Register (18h or 19h) is
set, CFAULT
will be asserted, when the fan fault input
pin for the corresponding fan is asserted (low)
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> If Bit 0 of an AIN Behavior Register is set
(50h AIN0, 51h AIN1), CFAULT
will be asserted if
the corresponding AIN high limit is exceeded
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> If Bit 4 of an AIN Behavior Register is set, CFAULT
will be asserted if an analog input crosses the
corresponding AIN low limit, the direction depending
on the setting of Bit 3 of the AIN Behavior Register.
(0 = CFAULT
when input goes below low limit,
1 = CFAULT
when input goes above low limit).
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