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参数资料
| 型号： | ADM1033ARQ |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/35页 |
| 文件大小： | 424K |
| 描述： | IC THERM/FAN SPEED CTRLR 16-QSOP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi Product Discontinuation Notice 25/Aug/2008 |
| 标准包装： | 98 |
| 功能： | 风扇控制，温度监控器 |
| 传感器类型： | 内部和外部 |
| 感应温度： | -40°C ~ 125°C，外部传感器 |
| 精确度： | ±1°C |
| 拓扑： | ADC，比较器，多路复用器，寄存器库 |
| 输出类型： | SMBus? |
| 输出警报： | 是 |
| 输出风扇： | 是 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 管件 |
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ADM1033
http://onsemi.com
12
Block Write
In this operation, the master device writes a block of data
to a slave address as follows. A maximum of 32 bytes can be
written.
1. The master asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by a write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address. The register
address sets up the address pointer register and
determines whether a block write (MSB = 1) or a
byte write (MSB = 0) takes place.
5. The slave asserts ACK on SDA.
6. The master sends the byte count.
7. The slave asserts ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts ACK on SDA after each byte.
10. The master asserts a stop condition on SDA to end
the transaction.
Figure 22. Block Write to RAM
SLAVE
ADDRESS
S
BYTE
COUNT
DATA 2
DATA 1
REGISTER
ADDRESS
W
A
A
P
A
A
A
DATA N
A
Read Operations
Receive Byte
This is useful when repeatedly reading a single register.
The register address must be set up prior to this, with the
MSB at 0 to read a single byte. In this operation, the master
device receives a single byte from a slave device as follows:
1. The master device asserts a start condition on
SDA.
2. The master sends the 7-bit slave address followed
by the read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master sends NO ACK on SDA.
6. The master asserts a stop condition on SDA, and
the transaction ends.
In the ADM1033, the receive byte protocol is used to read
a single byte from a register whose address has previously
been set by a send byte or write byte operation.
Figure 23. Receive Byte
SLAVE
ADDRESS
S
DATA
R
A
A
P
Block Read
In this operation, the master reads a block of data from a
slave device. The number of bytes to be read must be set in
advance. To do this, use a write byte operation to the
#Bytes/Block Read Register at Address 0x00. The register
address determines whether a block-read or a read-byte
operation is to be completed (set MSB to 1 to specify a
block-read operation). A maximum of 32 bytes can be read.
1. The master asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address (MSB = 1).
5. The slave asserts ACK on SDA.
6. The master asserts a repeated start on SDA.
7. The master sends the 7-bit slave address followed
by the read bit (high).
8. The slave asserts ACK on SDA.
9. The slave sends the byte count.
10. The master asserts ACK on SDA.
11. The slave sends N data bytes.
12. The master asserts ACK on SDA after each data
byte.
13. The master does not acknowledge after the Nth
data byte.
14. The master asserts a stop condition on SDA to end
the transaction.
Figure 24. Block Read from RAM
SLAVE
ADDRESS
S
BYTE
COUNT
DATA 1
REGISTER
ADDRESS
W
A
P
A
A
A DATA N
SLAVE
ADDRESS
S
R
A
A
SMBus Timeout
The ADM1033 has a programmable SMBus timeout
feature. When this is enabled, the SMBus typically times out
after 25 ms of no activity. The timeout is disabled by default.
It prevents hangups by releasing the bus after a period of
inactivity.
To enable the SDA timeout, set the SDA timeout bit
(Bit 5) of Configuration Register 1 (Address 0x01) to 1.
To enable the SCL timeout, set the SCL timeout bit (Bit 4)
of Configuration Register 1 (Address 0x01) to 1.
Packet Error Checking (PEC)
The ADM1033 also supports packet error checking
(PEC). This optional feature is triggered by the extra clock
for the PEC byte. The PEC byte is calculated using CRC-8.
The frame check sequence (FCS) conforms to CRC-8 by the
following:
(eq. 1)
C(x) + x
8
) x
2
) x ) 1
For more information, consult www.SMBus.org
.
Alert Response Address (ARA)
Figure 25. ALERT Response Address
ALERT RESPONSE
ADDRESS
S
DEVICE
ADDRESS
R
A
A
P
When multiple devices exist on the same bus, the ARA
feature allows an interrupting device to identify itself to the
host.
The ALERT
output can be used as an interrupt output or
as an SMBusALERT
. One or more ALERT
outputs can be
connected to a common SMBusALERT
line, connected to
the master.
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