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| 型号： | ADM1062ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/36页 |
| 文件大小： | 0K |
| 描述： | IC SEQUENCER/SUPERVISOR 40LFCSP |
| 标准包装： | 1 |
| 系列： | Super Sequencer® |
| 类型： | 序列发生器 |
| 监视电压数目： | 10 |
| 输出： | 可编程 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 托盘 |
| 配用： | EVAL-ADM1062TQEBZ-ND - BOARD EVALUATION FOR ADM1062TQ |
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ADM1062
COMMUNICATING WITH THE ADM1062
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1062 (undervoltage/overvoltage
thresholds, glitch filter timeouts, PDO configurations, and so on)
is dictated by the contents of the RAM. The RAM comprises
digital latches that are local to each of the functions on the device.
The latches are double-buffered and have two identical latches,
Latch A and Latch B. Therefore, when an update to a function
occurs, the contents of Latch A are updated first, and then the
contents of Latch B are updated with identical data. The advantages
Configuration section.
The two latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the EEPROM
(nonvolatile memory) to the local latches. This download occurs
in six steps, as follows:
With no power applied to the device, the PDOs are all
high impedance.
When 1.2 V appears on any of the inputs connected to the V DD
arbitrator (VH or VPx), the PDOs are all weakly pulled to
GND with a 20 kΩ resistor.
When the supply rises above the undervoltage lockout of the
device (UVLO is 2.5 V), the EEPROM starts to download
to the RAM.
The EEPROM downloads its contents to all Latch As.
When the contents of the EEPROM are completely downloaded
to the Latch As, the device controller signals all Latch As to
download to all Latch Bs simultaneously, completing the
configuration download.
At 0.5 ms after the configuration download completes, the first
state definition is downloaded from the EEPROM into the SE.
Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1062 to issue
a no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
the EEPROM into the RAM registers, the user may need to alter
the configuration of functions on the ADM1062, such as changing
the undervoltage or overvoltage limit of an SFD, changing the
fault output of an SFD, or adjusting the rise time delay of one of
the PDOs.
The ADM1062 provides several options that allow the user to
update the configuration over the SMBus interface. The following
three options are controlled in the UPDCFG register:
Option 1
Update the configuration in real time. The user writes to the RAM
across the SMBus, and the configuration is updated immediately.
Option 2
Update the Latch As without updating the Latch Bs. With this
method, the configuration of the ADM1062 remains unchanged
and continues to operate in the original setup until the instruction
is given to update the Latch Bs.
Option 3
Change the EEPROM register contents without changing the
RAM contents, and then download the revised EEPROM contents
to the RAM registers. With this method, the configuration of
the ADM1062 remains unchanged and continues to operate in
the original setup until the instruction is given to update the RAM.
The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents if
revisions to the configuration are unsatisfactory. For example,
if the user needs to alter an overvoltage threshold, the RAM
register can be updated, as described in Option 1. However,
if the user is not satisfied with the change and wants to revert to
the original programmed value, the device controller can issue
a command to download the EEPROM contents to the RAM
again, as described in Option 3, restoring the ADM1062 to its
original configuration.
The topology of the ADM1062 makes this type of operation
possible. The local, volatile registers (RAM) are all double-
buffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves
the double-buffered latches open at all times. If Bit 0 is set to 0
when a RAM write occurs across the SMBus, only the first side
of the double-buffered latch is written to. The user must then write
a 1 to Bit 1 of the UPDCFG register. This generates a pulse to
update all the second latches at once. EEPROM writes occur in
a similar way.
The final bit in this register can enable or disable EEPROM
page erasure. If this bit is set high, the contents of an EEPROM
page can all be set to 1. If this bit is set low, the contents of a
page cannot be erased, even if the command code for page
erasure is programmed across the SMBus. The bit map for the
UPDCFG register is shown in the AN-698 Application Note at
www.analog.com . A flow diagram for download at power-up
Rev. C | Page 27 of 36
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