参数资料
型号: ADM1064ACP
厂商: ANALOG DEVICES INC
元件分类: 电源管理
英文描述: Super Sequencer with Voltage Readback ADC
中文描述: 10-CHANNEL POWER SUPPLY SUPPORT CKT, QCC40
封装: 6 X 6 MM, MO-220-VJJD-2, LFCS-40
文件页数: 28/32页
文件大小: 523K
代理商: ADM1064ACP
ADM1064
Rev. 0 | Page 28 of 32
0
ASLAVE
S
W A
2
(BLOCK READ)
4
1
3
A
5
S
6
ASLAVE
7
BYTE
9
10
12
11
A
R A
8
D1
DATA
32
13
A
14
P
A
Figure 41. Block Read from EEPROM or RAM
Error Correction
The ADM1064 provides the option of issuing a PEC (packet
error correction) byte after a write to RAM, a write to
EEPROM, a block write to RAM/EEPROM, or a block read
from RAM/EEPROM. This enables the user to verify that the
data received by or sent from the ADM1064 is correct. The PEC
byte is an optional byte sent after that last data byte has been
written to or read from the ADM1064. The protocol is as
follows:
1.
The ADM1064 issues a PEC byte to the master. The master
checks the PEC byte and issues another block read, if the
PEC byte is incorrect.
2.
A no acknowledge (NACK) is generated after the PEC byte
to signal the end of the read.
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
C
(
x
) =
x
8
+
x
2
+
x
1
+ 1
See the SMBus 1.1 specification for details.
An example of a block read with the optional PEC byte is
shown in Figure 42.
0
ASLAVE
S
W A
2
(BLOCK READ)
4
1
3
A
5
S
6
ASLAVE
7
BYTE
9
10
12
11
A
R A
8
D1
DATA
32
A
13
PEC
14
A
15
P
A
Figure 42. Block Read from EEPROM or RAM with PEC
相关PDF资料
PDF描述
ADM1064ACP-REEL Super Sequencer with Voltage Readback ADC
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ADM1064ASU Super Sequencer with Voltage Readback ADC
ADM1064ASU-REEL Super Sequencer with Voltage Readback ADC
ADM1064ASU-REEL7 Super Sequencer with Voltage Readback ADC
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