参数资料
型号: ADM1064ACPZ
厂商: Analog Devices Inc
文件页数: 27/32页
文件大小: 0K
描述: IC SEQUENCER/SUPERVISOR 40-LFCSP
标准包装: 1
系列: Super Sequencer®
类型: 序列发生器
监视电压数目: 10
输出: 可编程
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP-VQ(6x6)
包装: 托盘
配用: EVAL-ADM1064TQEB-ND - BOARD EVALUATION FOR ADM1064TQ
ADM1064
?
To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erase. In this case, the
command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The only data byte is the low
byte of the EEPROM address, as shown in Figure 37.
7.
8.
9.
10.
The slave asserts an ACK on SDA.
The master sends N data bytes.
The slave asserts an ACK on SDA after each data byte.
The master asserts a stop condition on SDA to end the
transaction.
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2
3
4
5
6
7 8
1
2
3
4
5
6
7
8
9
10
S W A
W A COMMAND 0xFC A
A DATA A DATA A DATA A P
SLAVE
ADDRESS
EEPROM
ADDRESS
HIGH BYTE
(0xF8 TO 0xFB)
A
EEPROM
ADDRESS
LOW BYTE
(0x00 TO 0xFF)
A P
S
SLAVE
ADDRESS
(BLOCK WRITE)
BYTE
COUNT
1 2 N
Figure 37. Setting an EEPROM Address
Figure 39. Block Write to the EEPROM or RAM
?
Because a page consists of 32 bytes, only the three MSBs of
the address low byte are important for page erasure. The
lower five bits of the EEPROM address low byte specify the
addresses within a page and are ignored during an erase
operation.
To write a single byte of data to the EEPROM. In this case,
the command byte is the high byte of EEPROM Address
0xF8 to EEPROM Address 0xFB. The first data byte is the
low byte of the EEPROM address, and the second data byte
is the actual data, as shown in Figure 38.
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except when
There must be at least N locations from the start address to the
highest EEPROM address (0xFBFF) to avoid writing to
invalid addresses.
An address crosses a page boundary. In this case, both pages
must be erased before programming.
Note that the ADM1064 features a clock extend function for
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5
6
7
8
9 10
writes to EEPROM. Programming an EEPROM byte takes
S W A
SLAVE
ADDRESS
EEPROM
ADDRESS
HIGH BYTE
(0xF8 TO 0xFB)
A
EEPROM
ADDRESS
LOW BYTE
(0x00 TO 0xFF)
A DATA A P
approximately 250 μs, which limits the SMBus clock for
repeated or block write operations. The ADM1064 pulls SCL
low and extends the clock pulse when it cannot accept any
Figure 38. Single Byte Write to the EEPROM
Block Write
In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
have been set previously. In the ADM1064, a send byte opera-
tion sets a RAM address, and a write byte/word operation sets
an EEPROM address, as follows:
more data.
READ OPERATIONS
The ADM1064 uses the following SMBus read protocols.
Receive Byte
In a receive byte operation, the master device receives a single
byte from a slave device, as follows:
1.
2.
3.
4.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by
the write bit (low).
The addressed slave device asserts an ACK on SDA.
The master sends a command code that tells the slave
device to expect a block write. The ADM1064 command
code for a block write is 0xFC (1111 1100).
1.
2.
3.
4.
5.
6.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The addressed slave device asserts an ACK on SDA.
The master receives a data byte.
The master asserts a NACK on SDA.
The master asserts a stop condition on SDA, and the
5.
6.
The slave asserts ACK on SDA.
The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
transaction ends.
In the ADM1064, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation, as shown in Figure 40.
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2
3
4
5
6
S
SLAVE
ADDRESS
R
A
DATA
A
P
Figure 40. Single Byte Read from the EEPROM or RAM
Rev. D | Page 27 of 32
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