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| 型号： | ADM1088AKS-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | IC SIMPLE SEQUENCER P-P SC70-6 |
| 标准包装： | 1 |
| 系列： | Simple Sequencers® |
| 类型： | 序列发生器 |
| 监视电压数目： | 1 |
| 输出： | 推挽式，图腾柱 |
| 复位： | 低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-TSSOP，SC-88，SOT-363 |
| 供应商设备封装： | SC-70-6 |
| 包装： | 剪切带 (CT) |
| 其它名称： | ADM1088AKSREEL7CT |
ADM1085/ADM1086/ADM1087/ADM1088
CIRCUIT INFORMATION
TIMING CHARACTERISTICS AND TRUTH TABLES
The enable outputs of the ADM1085/ADM1086/ADM1087/
ADM1088 are related to the V IN and enable inputs by a simple
AND function. The enable output is asserted only if the enable
input is asserted and the voltage at V IN is above V TH_RISING , with
the time delay elapsed. Table 5 and Table 6 show the enable
output logic states for different V IN /enable input combinations
when the capacitor delay has elapsed. The timing diagrams in
the ADM1085/ADM1086/ADM1087/ADM1088 enable outputs
respond to V IN and enable input signals.
Table 5. ADM1085/ADM1086 Truth Table
When V IN reaches the upper threshold voltage (V TH_RISING ), an
internal circuit generates a delay (t EN ) before the enable output
is asserted. If V IN drops below the lower threshold voltage
(V TH_FALLING ), the enable output is deasserted immediately.
Similarly, if the enable input is disabled while V IN is above the
threshold, the enable output deasserts immediately. Unlike V IN ,
a low-to-high transition on ENIN (or high-to-low on ENIN)
does not yield a time delay on ENOUT (ENOUT).
CAPACITOR-ADJUSTABLE DELAY CIRCUIT
delay on the enable output. A 250 nA current source charges a
V IN
<V TH_FALLING
<V TH_FALLING
>V TH_RISING
>V TH_RISING
ENIN
0
1
0
1
ENOUT
0
0
0
1
small internal parasitic capacitance (C INT ). When the capacitor
voltage reaches 1.2 V, the enable output is asserted. The time
taken for the capacitor to reach 1.2 V, in addition to the propa-
gation delay of the comparator, constitutes the enable timeout,
which is typically 35 μs.
To minimize the delay between V IN falling below V TH_FALLING
Table 6. ADM1087/ADM1088 Truth Table
V IN ENIN
<V TH_FALLING 1
<V TH_FALLING 0
>V TH_RISING 1
ENOUT
1
1
1
and the enable output deasserting, an NMOS transistor is
connected in parallel with C INT . The output of the voltage
detector is connected to the gate of this transistor so that, when
V IN falls below V TH_FALLING , the transistor switches on and C INT
discharges quickly.
>V TH_RISING
0
0
V CC
V IN
V TH_RISING
V TH_FALLING
SIGNAL FROM
VOLTAGE
DETECTOR
C INT
250nA
1.2V
TO AND GATE
AND OUTPUT
STAGE
ENIN
C
CEXT
ENOUT
t EN
Figure 18. ADM1085/ADM1086 Timing Diagram
Figure 20. Capacitor-Adjustable Delay Circuit
Connecting an external capacitor to the CEXT pin delays the
rise time—and therefore the enable timeout—further. The
relationship between the value of the external capacitor and the
V IN
V TH_RISING
V TH_FALLING
resulting timeout is characterized by the following equation:
t EN = ( C × 4.8 ×10 6 ) + 35 μs
ENIN
ENOUT
t EN
Figure 19. ADM1087/ADM1088 Timing Diagram
Rev. A | Page 9 of 16
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