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参数资料
| 型号： | ADM1171-2AUJZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/16页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR HOTSWAP 16.5V TSOT-23-8 |
| 产品培训模块： | Hot Swap Design |
| 标准包装： | 1 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 2.7 V ~ 16.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-8 薄型，TSOT-23-8 |
| 供应商设备封装： | TSOT-23-8 |
| 包装： | 标准包装 |
| 产品目录页面： | 792 (CN2011-ZH PDF) |
| 配用： | EVAL-ADM1171EBZ-ND - BOARD EVALUATION FOR ADM1171 |
| 其它名称： | ADM1171-2AUJZ-RL7DKR |
ADM1171
threshold. The device can be reset by toggling the ON-CLR pin
the TIMER pin activates the 2 μA pull-down once the 1.3 V
threshold is reached, and continues to pull down until it reaches
I RSENSE
5μA
Data Sheet
the 0.2 V threshold. At this point, the 100 μA pull-down is
activated and the GATE pin is enabled. The device keeps
The duty cycle of this automatic retry cycle is set to the ratio of
2 μA/60 μA, which approximates 3.8% on. The value of the
timer capacitor determines the on time of this cycle. This time
is calculated as follows:
t ON = 1.3 × C TIMER /60 μA
V TIMER
V GSFET
V OUT
60μA
SHORT-
CIRCUIT
EVENT
COMP2
t OFF = 1.1 × C TIMER /2 μA
Figure 39. ADM1171-2 Latch Off After Overcurrent Fault
I RSENSE
SOFT START
2μA
The inrush current profile is controlled using an external
capacitor on the soft start (SS) pin. During power-on reset, the
V TIMER
60μA
SS pin is held at GND. When the pass FET begins to conduct
V GSFET
100μA
current, a pull-up current source is initiated on the SS pin and
charges the voltage on the soft start capacitor in a linear fashion.
The current limit of the device is porportional to the voltage on
V OUT
SHORT-
CIRCUIT
EVENT
the SS pin until it reaches 1 V. When the voltage on the SS pin
reaches 1 V, the current limit reaches the normal operating
condition of V SENSE = 50 mV. The voltage on the SS pin continues
COMP2
FAULT
COMP1
FAULT
to rise past the 1 V level with no effect on the current limit. The
reference voltage for the GATE linear control amplifier is derived
CYCLE CYCLE
Figure 38. ADM1171-1 Automatic Retry During Overcurrent Fault
AUTOMATIC RETRY OR LATCHED OFF
The ADM1171 is available in two models. The ADM1171-1
has an automatic retry system whereby when a current fault is
detected, the FET is shut down after a time determined by the
timer capacitor, and it is switched on again in a controlled con-
for details). The period of this cycle is determined by the timer
capacitor at a duty cycle of 3.8% on and 96.2% off.
The ADM1171-2 model has a latch off system whereby when a
current fault is detected, the GATE is switched off after a time
determined by the timer capacitor (see Figure 39 for details).
Toggling the ON-CLR pin, or pulling the TIMER pin to GND
for a brief period, resets this condition.
from the soft start voltage, such that the inrush linear current
limit is defined as
I LIMIT = V SS /(20 × R SENSE )
This provides a limit of 50 mV across R SENSE when V SS is at 1 V.
Therefore, the value for the SS capacitor is chosen as follows:
C SS = I SS × t
where I SS = 10 μA and t is the time required for the current limit
to ramp up.
CSOUT PIN
The ADM1171 has a current sense output pin (CSOUT). The
CSOUT pin provides an analog voltage representing the current
flowing through the sense resistor. The voltage drop across the
sense resistor, as equated by V CC ? SENSE, is gained up by a
factor of 20 and presented on the CSOUT pin. The output
impedance of the pin is typically 14 kΩ.
Rev. A | Page 14 of 16
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