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参数资料
| 型号： | ADM1185ARMZ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 电源管理 |
| 英文描述： | Quad Voltage Monitor and Sequencer |
| 中文描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10 |
| 封装： | LEAD FREE, MSOP-10 |
| 文件页数： | 5/12页 |
| 文件大小： | 226K |
| 代理商： | ADM1185ARMZ |
Preliminary Technical Data
ADM1185
PIN CONFIGURATIONS
Rev. PrK | Page 5 of 12
1
2
3
4
ADM1185
TOP VIEW
(NOT TO SCALE)
Vcc
OUT1
OUT2
OUT3
PWRGD
5
10
9
8
7
6
VIN4
VIN2
VIN1
VIN3
GND
Figure 3. Pin Configurations
PIN FUNCTIONAL DESCRIPTIONS
Table 3.
Pin No.
Name
1
GND
2
VIN1
Description
Chip Ground Pin.
Non-inverting input of comparator 1. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.
Non-inverting input of comparator 2. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.
Non-inverting input of comparator 3. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.
Non-inverting input of comparator 4. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.
Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN4 is greater than 0.6V. A time delay of 190ms (typical) is included before assertion of this
pin. After power-up (after PWRGD asserts) this output will be driven low if any of the voltages on the VIN1-
VIN4 pins falls below 0.6V.
Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN3 is greater than 0.6V. After power-up (after PWRGD asserts) this output will be driven low
if the voltage on VIN1 falls below 0.6V.
Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN2 is greater than 0.6V. After power-up (after PWRGD asserts) this output will be driven low
if the voltage on VIN1 falls below 0.6V.
Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN1 is greater than 0.6V. A time delay of 190ms (typical) is included before assertion of this
pin. After power-up (after PWRGD asserts) this output will be driven low if the voltage on VIN1 falls below
0.6V.
Positive supply input pin. The operating supply voltage range is 2.7 V to 5.5 V.
3
VIN2
4
VIN3
5
VIN4
6
PWRGD
7
OUT3
8
OUT2
9
OUT1
10
VCC
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