参数资料
型号: ADM13305-33ARZ
厂商: Analog Devices Inc
文件页数: 5/12页
文件大小: 0K
描述: IC SUPERVISOR DUAL 5/3.3V 8SOIC
产品培训模块: Voltage Supervisor 101
标准包装: 98
类型: 多压监控器
监视电压数目: 2
输出: 推挽式,图腾柱
复位: 高有效/低有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.93V,4.55V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 管件
产品目录页面: 800 (CN2011-ZH PDF)
ADM13305
TIMING REQUIREMENTS
V DD = 2.7 V to 5.5 V, R L = 1 MΩ, C L = 50 pF, T A = 25°C.
Table 3. ADM13305-18, ADM13305-25 and ADM13305-33
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PULSE WIDTH (t w )
SENSEv
MR
WDI
6
100
100
μs
ns
ns
V SENSEvL = V IT? ? 0.3 V, V SENSEvH = V IT+ + 0.3 V
V IH = 0.7 × V DD , V IL = 0.3 × V DD
V IH = 0.7 × V DD , V IL = 0.3 × V DD
Table 4. ADM13305-4 and ADM13305-5
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PULSE WIDTH (t w )
SENSEv
MR
WDI
100
100
30
μs
ns
ns
V SENSEvL = V IT? ? 0.3 V, V SENSEvH = V IT+ + 0.3 V
V IH = 0.7 × V DD , V IL = 0.3 × V DD
V IH = 0.7 × V DD , V IL = 0.3 × V DD
SWITCHING CHARACTERISTICS
V DD = 2.7 V to 5.5 V, R L = 1 MΩ, C L = 50 pF, T A = 25°C.
Table 5. ADM13305-18, ADM13305-25 and ADM13305-33
Parameter
Watchdog Timeout (t t(OUT) )
Delay Time (t d )
Propagation Delay, High-to-Low, MR to RESET 1 /RESET (t PHL )
Propagation Delay, Low-to-High, MR to RESET/RESET 1 (t PLH )
Propagation Delay, High-to-Low, SENSEv to RESET 1 /RESET (t PHL )
Propagation Delay, Low-to-High, SENSEv to RESET/RESET 1 (t PLH )
Min
1.1
140
Typ
1.6
200
200
200
1
1
Max
2.3
280
500
500
5
5
Unit
sec
ms
ns
ns
μs
μs
Test Conditions/Comments
V I(SENSEv) ≥ V IT+ + 0.2 V, MR ≥ 0.7 × V DD
V I(SENSEv) ≥ V IT+ + 0.2 V, MR ≥ 0.7 × V DD
V I(SENSEv) ≥ V IT+ + 0.2 V, V IH ≥ 0.7 × V DD , V IL ≥ 0.3 × V DD
V I(SENSEv) ≥ V IT+ + 0.2 V, V IH ≥ 0.7 × V DD , V IL ≥ 0.3 × V DD
V IH = V IT+ + 0.3 V, V IL = V IT? ? 0.3 V, MR ≥ 0.7 × V DD
V IH = V IT+ + 0.3 V, V IL = V IT? ? 0.3 V, MR ≥ 0.7 × V DD
1
The reset timeout delay of 200 ms masks the propagation delay.
Table 6. ADM13305-4 and ADM13305-5
Parameter
Watchdog Timeout (t t(out) )
Delay Time (t d )
Propagation Delay, High-to-Low, MR to RESET 1 /RESE T (t PHL )
Propagation Delay, Low-to-High, MR to RESET/RESET 1 (t PLH )
Propagation Delay, High-to-Low, SENSEv to RESET 1 /RESET (t PHL )
Propagation Delay, Low-to-High, SENSEv to RESET/RESET 1 (t PLH )
Min
1.1
140
Typ
1.6
200
200
200
30
30
Max
2.3
280
500
500
Unit
sec
ms
ns
ns
μs
μs
Test Conditions/Comments
V I(SENSEv) ≥ V IT+ + 0.2 V, MR ≥ 0.7 × V DD
V I(SENSEv) ≥ V IT+ + 0.2 V, MR ≥ 0.7 × V DD
V I(SENSEv) ≥ V IT+ + 0.2 V, V IH ≥ 0.7 × V DD , V IL ≥ 0.3 × V DD
V I(SENSEv) ≥ V IT+ + 0.2 V, V IH ≥ 0.7 × V DD , V IL ≥ 0.3 × V DD
V IH = V IT+ + 0.3 V, V IL = V IT? ? 0.3 V, MR ≥ 0.7 × V DD
V IH = V IT+ + 0.3 V, V IL = V IT? ? 0.3 V, MR ≥ 0.7 × V DD
1
The reset timeout delay of 200 ms masks the propagation delay.
FUNCTIONAL TRUTH TABLE
Table 7.
MR
L
H
H
H
H
SENSE1 > V IT1
0
0
1
1
SENSE2 > V IT2
0
1
0
1
RESET
L
L
L
L
H
RESET
H
H
H
H
L
1
X = don’t care.
Rev. 0 | Page 5 of 12
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