参数资料
型号: ADM4852ARZ
厂商: Analog Devices Inc
文件页数: 1/16页
文件大小: 0K
描述: IC TXRX RS-485422 2.5MBPS 8-SOIC
标准包装: 98
类型: 收发器
驱动器/接收器数: 1/1
规程: RS422,RS485
电源电压: 4.75 V ~ 5.25 V
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 管件
产品目录页面: 790 (CN2011-ZH PDF)
5 V, Slew-Rate Limited, Half-Duplex and
Full-Duplex RS-485/RS-422 Transceivers
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2004–2012 Analog Devices, Inc. All rights reserved.
FEATURES
EIA RS-485-/RS-422-compliant
Data rate options
ADM4850/ADM4854: 115 kbps
ADM4851/ADM4855: 500 kbps
ADM4852/ADM4856: 2.5 Mbps
ADM4853/ADM4857: 10 Mbps
Half- and full-duplex options
Reduced slew rates for low EMI
True fail-safe receiver inputs
5 μA (maximum) supply current in shutdown mode
Up to 256 transceivers on one bus
Outputs high-Z when disabled or powered off
7 V to +12 V bus common-mode range
Thermal shutdown and short-circuit protection
Pin-compatible with the MAX308x
Specified over the 40°C to +85°C temperature range
Available in 8-lead SOIC, LFCSP, and MSOP packages
Qualified for automotive applications
APPLICATIONS
Low power RS-485 applications
EMI-sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
FUNCTIONAL BLOCK DIAGRAMS
04
93
1-
00
1
RO
RE
R
DE
DI
D
A
B
GND
VCC
ADM4850/ADM4851/
ADM4852/ADM4853
Figure 1.
04
93
1-
02
8
RO
R
A
B
DI
D
Z
Y
GND
VCC
ADM4854/ADM4855/
ADM4856/ADM4857
Figure 2.
GENERAL DESCRIPTION
ADM4855/ADM4856/ADM4857 are differential line transceivers
suitable for high speed half- and full-duplex data communication on
multipoint bus transmission lines. They are designed for balanced
data transmission and comply with EIA Standards RS-485 and
duplex transceivers that share differential lines and have separate
enable inputs for the driver and receiver. The full-duplex
dedicated differential line driver outputs and receiver inputs.
The parts have a 1/8-unit-load receiver input impedance, which
allows up to 256 transceivers on one bus. Because only one driver
should be enabled at any time, the output of a disabled or pow-
ered-down driver is three-stated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which ensures
a logic high output level when the inputs are open or shorted.
This guarantees that the receiver outputs are in a known state
before communication begins and when communication ends.
The driver outputs are slew-rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or by output
shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the commercial and industrial
temperature ranges and are available in 8-lead SOIC, LFCSP
(ADM4850 only) packages.
Table 1. Selection Table
Part No.
Half-/Full-Duplex
Data Rate
Half
115 kbps
Half
500 kbps
Half
2.5 Mbps
Half
10 Mbps
Full
115 kbps
Full
500 kbps
Full
2.5 Mbps
Full
10 Mbps
相关PDF资料
PDF描述
AA3FB CONN PLUG FEMALE 3PIN 15A
ADM4856ARZ IC TXRX RS485/422 2.5MBPS 8SOIC
VE-J1Y-MW-F3 CONVERTER MOD DC/DC 3.3V 66W
09BL4M CONN DIN MALE PLUG 4POS STR
VI-254-IW-F3 CONVERTER MOD DC/DC 48V 100W
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