参数资料
型号: ADM6384YKS29D3-RL7
厂商: ANALOG DEVICES INC
元件分类: 电源管理
英文描述: Microprocessor Supervisory Circuit in 4-Lead SC70
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO4
封装: EIAJ, SC-82, SC-70, 4 PIN
文件页数: 9/12页
文件大小: 137K
代理商: ADM6384YKS29D3-RL7
ADM6384
CIRCUIT DESCRIPTION
The ADM6384 provides microprocessor supply voltage
supervision by controlling the microprocessor’s reset input.
Code execution errors are avoided during power-up, power-
down, and brownout conditions by asserting a reset signal
when the supply voltage is below a preset threshold. In addition,
the ADM6384 allows supply voltage stabilization with a fixed
timeout before the reset deasserts after the supply voltage
rises above the threshold. If the user detects a problem with
the system’s operation, a manual reset input is available to reset
the microprocessor by means of an external push-button,
for example.
Rev. 0 | Page 9 of 12
V
CC
1V
V
CC
0V
V
TH
V
TH
V
CC
RESET
t
RD
t
RP
0
Figure 12. Reset Timing Diagram
MANUAL RESET INPUT
The ADM6384 features a manual reset input (MR) which, when
driven low, asserts the reset output. When MR transitions from
low to high, reset remains asserted for the duration of the reset
active timeout period before deasserting. The
52 kΩ internal pull-up so that the input is always high when
unconnected. An external push-button switch can be connected
between
MR and ground so that the user can generate a reset.
Debounce circuitry for this purpose is integrated on-chip. Noise
immunity is provided on the
MR input, and fast, negative-going
transients of up to 100 ns (typ) are ignored. A 0.1 μF capacitor
between
MR and ground provides additional noise immunity.
RESET OUTPUT
The ADM6384 features an active-low push-pull reset output.
The reset signal is guaranteed to be logic low for V
CC
down
to 1 V.
MR input has a
The reset output is asserted when V
CC
is below the reset
threshold (V
asserted for the duration of the reset active timeout period
(t
transitions from low to high. Figure 12 illustrates the behavior
of the reset outputs.
TH
) or when MR is driven low. Reset remains
RP
) after V
CC
rises above the reset threshold or after MR
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