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参数资料
| 型号： | ADM6384YKS39D2Z-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR MPU RESET SC70-4 |
| 标准包装： | 1 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 推挽式，图腾柱 |
| 复位： | 低有效 |
| 复位超时： | 最小为 20 ms |
| 电压 - 阀值： | 3.9V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SC-82A，SOT-343 |
| 供应商设备封装： | SC-70-4 |
| 包装： | 标准包装 |
| 其它名称： | ADM6384YKS39D2Z-R7DKR |
ADM6384
CIRCUIT DESCRIPTION
The ADM6384 provides microprocessor supply voltage supervi-
sion by controlling the microprocessor reset input. Code execution
errors are avoided during power-up, power-down, and brownout
conditions by asserting a reset signal when the supply voltage is
below a preset threshold. In addition, the ADM6384 allows
V CC
RESET
V CC
1V
0V
V CC
0V
V TH
t RP
V TH
t RD
supply voltage stabilization with a fixed timeout before the reset
deasserts after the supply voltage rises above the threshold. If the
user detects a problem with the system operation, a manual reset
input is available to reset the microprocessor by means of an
external push-button, for example.
RESET OUTPUT
The ADM6384 features an active-low, push-pull reset output.
The reset signal is guaranteed to be logic low for V CC down to 1 V.
The reset output is asserted when V CC is below the reset threshold
(V TH ) or when MR is driven low. Reset remains asserted for the
duration of the reset active timeout period (t RP ) after V CC rises
above the reset threshold or after MR transitions from low to high.
Figure 12. Reset Timing Diagram
MANUAL RESET INPUT
The ADM6384 features a manual reset input (MR) that, when
driven low, asserts the reset output. When MR transitions from
low to high, reset remains asserted for the duration of the reset
active timeout period before deasserting. The MR input has a
52 k? internal pull-up so that the input is always high when
unconnected. An external push-button switch can be connected
between MR and ground so that the user can generate a reset.
Debounce circuitry for this purpose is integrated on-chip. Noise
immunity is provided on the MR input, and fast, negative-going
transients of up to 100 ns (typical) are ignored. A 0.1 μF capacitor
between MR and ground provides additional noise immunity.
Rev. C | Page 9 of 12
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