参数资料
型号: ADM6819ARJZ-REEL7
厂商: Analog Devices Inc
文件页数: 7/12页
文件大小: 0K
描述: IC POWER SEQUENCER SOT23-6
标准包装: 1
系列: Simple Sequencers®
应用: 电源序列发生器
电源电压: 0.9 V ~ 5.5 V
电流 - 电源: 350µA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-6
供应商设备封装: SOT-23-6
包装: 标准包装
产品目录页面: 788 (CN2011-ZH PDF)
其它名称: ADM6819ARJZ-REEL7DKR

ADM6819/ADM6820
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V CC1 1
6
V CC2
V CC1 1
6
V CC2
ADM6819
ADM6820
GND 2
TOP VIEW
5
GATE
GND 2
TOP VIEW
5
GATE
(Not to Scale)
(Not to Scale)
SETV 3
4
EN
SETV 3
4
SETD
Figure 6. ADM6819 Pin Configuration
Table 4. Pin Function Descriptions
Pin Number
Figure 7. ADM6820 Pin Configuration
ADM6819
1
ADM6820
1
Mnemonic
V CC1
Description
Supply Voltage 1. Either V CC1 or V CC2 must be greater than the UVLO to enable external
FET Drive.
2
3
2
3
GND
SETV
Chip Ground Pin.
Sequenced Threshold Set. Connect to an external resistor divider to set the V CC1
threshold that enables GATE turn-on. The internal reference is 0.618 V.
4
EN
Active-High Enable. GATE drive is enabled t DELAY after EN is driven high. GATE drive is
immediately disabled when EN is driven low. Connect this pin to the higher of V CC1 or
V CC2 if not used. EN is internally identical to SETV (0.618 V threshold) and, therefore, can
be used as a second supply monitor, enabling two supplies to be validated before
sequencing begins.
4
SETD
GATE Delay Set Input. Connect an external capacitor from SETD to GND to adjust the
delay from SETV > V TH to GATE turn-on. t DELAY (s) = 2.652 × 10 6 × C SET (F).
5
5
GATE
GATE Drive Output. GATE drives an external N-channel FET to connect V CC2 to the load.
GATE drive enables t DELAY after SETV exceeds V TH and ENABLE is driven high. GATE drive is
immediately disabled when SETV drops below V TH or ENABLE is driven low. When
enabled, an internal charge pump drives GATE above V CCX to fully enhance the external
N-channel FET.
6
6
V CC2
Supply Voltage 2. Either V CC1 or V CC2 must be greater than the UVLO to enable the
external FET Drive.
Rev. 0 | Page 7 of 12
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