参数资料
型号: ADM691AR-REEL
厂商: Analog Devices Inc
文件页数: 11/12页
文件大小: 0K
描述: IC SUPER MPU 4.65 250MA 16SOIC
标准包装: 1,000
类型: 备用电池电路
监视电压数目: 1
输出: 开路漏极,推挽式
复位: 高有效/低有效
复位超时: 最小为 35 ms
电压 - 阀值: 4.65V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 带卷 (TR)
其它名称: ADM691AR-REELTR
ADM691A/ADM693A/ADM800L/M
RAM Write Protection
The CE OUT line drives the Chip Select inputs of the CMOS
RAM. CE OUT follows CE IN as long as V CC is above the reset
threshold. If V CC falls below the reset threshold, CE OUT goes
high, independent of the logic level at CE IN . This prevents the
microprocessor from writing erroneous data into RAM during
power-up, power-down, brownouts and momentary power in-
terruptions. The LOW LINE output goes low when V CC falls
below the reset threshold.
RESET also goes low if the Watchdog Timer is enabled and
WDI remains either high or low for longer than the watchdog
timeout period.
The RESET output has an internal 1.6 mA pullup, and can ei-
ther connect to an open collector RESET bus or directly drive a
CMOS gate without an external pullup resistor.
INPUT POWER
+5V
Watchdog Timer
0.1μF
0.1μF
CE OUT
ADM800M
PFO
RESET
μP
The microprocessor drives the WATCHDOG INPUT (WDI)
with an I/O line. When OSC IN and OSC SEL are uncon-
nected, the microprocessor must toggle the WDI pin once every
1.6 seconds to verify proper software execution. If a hardware or
softwar e failure occurs such that WDI not toggled a 200 ms
RESET pulse will be generated after 1.6 seconds. This typi-
cally restarts the microprocessor’s power-up routine. A new
RESET pulse is issued every 1.6 seconds until WDI is again
strobed.
The WATCHDOG OUTPUT ( WDO ) goes low if the watch-
R1
R2
3V
BATTERY
NC
V CC BATT V OUT
ON
V BATT
ADM691A
ADM693A CE IN
ADM800L
PFI
GND
WDI
OSC IN
OSC SEL
LOW LINE WDO
RESET
CMOS
RAM
ADDRESS
DECODE
0.1μF
A0–A15
I/O LINE
NMI
RESET
dog timer is not serviced within its timeout period. Once WDO
goes low it remains low until a transition occurs at WDI. The
watchdog timer feature can be disabled by leaving WDI uncon-
nected. OSC IN and OSC SEL also allow other watchdog tim-
ing options.
REV. 0
–11 –
SYSTEM STATUS
INDICATORS
Figure 24. Typical Application Circuit
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