参数资料
型号: ADM696SQ
厂商: Analog Devices Inc
文件页数: 2/12页
文件大小: 0K
描述: IC SUPERVISOR MPU 100MA 16CDIP
标准包装: 25
类型: 备用电池电路
监视电压数目: 1
输出: 推挽式,推挽式
复位: 高有效/低有效
复位超时: 最小为 35 ms
电压 - 阀值: 1.3V
工作温度: -55°C ~ 125°C
安装类型: 通孔
封装/外壳: 16-CDIP(0.300",7.62mm)
供应商设备封装: 16-CDIP
包装: 管件
ADM696/ADM697–SPECIFICATIONS
(V CC = Full Operating Range, V BATT = +2.8 V, T A = T MIN to T MAX
unless otherwise noted.)
P arameter
V CC Operating Voltage Range
V BATT Operating Voltage Range
Min
3.0
2.0
Typ
Max
5.5
V CC – 0 3
Units
V
V
Test Conditions/Comments
BATTERY BACKUP SWITCHING (ADM696)
V OUT Output Voltage
V OUT in Battery Backup Mode
Supply Current (Excludes I OUT )
Supply Current in Battery Backup Mode
Battery Standby Current
(+ = Discharge, – = Charge)
Battery Switchover Threshold
V CC – V BATT
Battery Switchover Hysteresis
BATT ON Output Voltage
V CC – 0.05
V CC – 0.5
V BATT – 0.05
–0.1
–1
V CC – 0.025
V CC – 0.25
V BATT – 0.02
1 1.95
0.6 1
+0.02
+0.02
70
50
20
0.4
V
V
V
mA
μ A
μ A
μ A
mV
mV
mV
V
I OUT = 1 mA
I OUT ≤ 100 mA
I OUT = 250 μ A, V CC < V BATT – 0.2 V
I OUT = 100 mA
V CC = 0 V, V BATT = 2.8 V
5.5 V > V CC > V BATT + 0.2 V
T A = +25 ° C
Power-Up
Power-Down
I SINK = 1.6 mA
BATT ON Output Short Circuit Current
0.5
7
1
25
mA
μ A
BATT ON = V OUT = 2.4 V Sink Current
BATT ON = V OUT , V CC = 0 V, Source Current
RESET AND WATCHDOG TIMER
Low Line Threshold (LL IN )
Reset Timeout Delay
Watchdog Timeout Period, Internal Oscillator
Watchdog Timeout Period, External Clock
Minimum WDI Input Pulse Width
RESET Output Voltage @ V CC = +1 V
RESET, RESET Output Voltage
LOW LINE , WDO Output Voltage
Output Short Circuit Source Current
1.25
35
1.0
70
4032
960
50
3.5
3.5
1
1.3
50
1.6
100
4
3
1.35
70
2.25
140
4097
1025
200
0.4
0.4
0.4
25
V V CC = +5 V, +3 V
ms OSC SEL = HIGH, V CC = 5 V, T A = +25 ° C
s Long Period, V CC = 5 V, T A = +25 ° C
ms Short Period, V CC = 5 V, T A = +25 ° C
Cycles Long Period
Cycles Short Period
ns V IL = 0.4, V IH = 3.5 V, V CC = 5 V
mV I SINK = 10 μ A, V CC = 1 V
V I SINK = 400 μ A, V CC = 2 V, V BATT = 0 V
V I SINK = 1.6 mA, 3 V < V CC < 5.5 V
V I SOURCE = 1 μ A, V CC = 5 V
V I SINK = 1.6 mA,
V I SOURCE = 1 μ A, V CC = 5 V
μ A
WDI Input Threshold
V CC = 5 V 1
Logic Low
0.8
V
Logic High
WDI Input Current
3.5
–50
20
–15
50
V
μ A WD1 = V OUT , (V CC ) T A = +25 ° C
μ A WD1 = 0 V, T A = +25 ° C
POWER FAIL DETECTOR
PFI Input Threshold
PFI–LL IN Threshold Difference
PFI Input Current
LL IN Input Current
PFO Output Voltage
PFO Short Circuit Source Current
1.2
–50
–25
–50
3.5
1
1.3
± 15
± 0.01
± 0.01
3
1.4
+50
+25
+50
0.4
25
V
mV
nA
nA
V
V
μ A
V CC = +3 V, +5 V
V CC = +3 V, +5 V
I SINK = 1.6 mA
I SOURCE = 1 μ A, V CC = 5 V
PFI = Low, PFO = 0 V
CHIP ENABLE GATING (ADM697)
CE IN Threshold
0.8
V
V IL
CE IN Pullup Current
CE OUT Output Voltage
CE Propagation Delay
OSCILLATOR
OSC IN Input Current
OSC SEL Input Pullup Current
OSC IN Frequency Range
OSC IN Frequency with Ext. Capacitor
3.0
V CC – 0.5
0
3
5
± 2
5
4
0.4
25
250
V
μ A
V
V
ns
μ A
μ A
kHz
kHz
V IH , V CC = 5 V
I SINK = 1.6 mA
I SOURCE = 800 μ A
OSC SEL = 0 V
OSC SEL = 0 V, C OSC = 47 pF
NOTE
1
WDI is a three-level input which is internally biased to 38% of V CC and has an input impedance of approximately 125 k ? .
Specifications subject to change without notice.
–2 –
REV. 0
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