参数资料
型号: ADM706RAR-REEL7
厂商: Analog Devices Inc
文件页数: 6/16页
文件大小: 0K
描述: IC SUPERVISOR MPU 2.63V WD 8SOIC
产品培训模块: Voltage Supervisor 101
标准包装: 1,000
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 160 ms
电压 - 阀值: 2.63V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 带卷 (TR)

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
MR 1
V CC 2
ADM706P
8
7
WDO
RESET
MR 1
V CC 2
ADM706R/
ADM706S/
8
7
WDO
RESET
GND 3 TOP VIEW 6 WDI
PFI 4 (Not to Scale) 5 PFO
GND 3
PFI 4
ADM706T
TOP VIEW
(Not to Scale)
6
5
WDI
PFO
Figure 3. ADM706P
Figure 4. ADM706R/ADM706S/ADM706T
Table 3. Pin Function Descriptions ADM706P/ADM706R/ADM706S/ADM706T
Pin No.
1
2
3
4
5
6
7 (ADM706R/ADM706S/
ADM706T Only)
7 (ADM706P Only)
8
Mnemonic
MR
V CC
GND
PFI
PFO
WDI
RESET
RESET
WDO
Description
Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven
from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An
internal 70 μA pull-up current holds the input high when floating.
Power Supply Input.
Ground. Ground reference for all signals (0 V).
Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less
than 1.25 V, PFO goes low. If unused, PFI should be connected to GND.
Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI is
less than 1.25 V.
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout
period, the watchdog output, WDO, goes low. The timer resets with each transition at the WDI
input. Either a high-to-low or a low-to-high transition clears the counter. The internal timer is
also cleared whenever reset is asserted.
Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by V CC being
below the reset threshold or by a low signal on the MR input. RESET remains low whenever V CC
is below the reset threshold. It remains low for 200 ms after V CC goes above the reset threshold
or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is
connected to MR.
Logic Output. RESET is an active high output suitable for systems that use active high reset
logic. It is the inverse of RESET.
Watchdog Output. WDO goes low if the internal watchdog timer times out as a result of
inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO also goes
low during low line conditions. Whenever V CC is below the reset threshold, WDO remains low. As
soon as V CC goes above the reset threshold, WDO goes high immediately.
Rev. C | Page 6 of 16
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