参数资料
型号: ADM706TAR
厂商: Analog Devices Inc
文件页数: 11/16页
文件大小: 0K
描述: IC SUPERVISOR MPU 3.08 WD 8SOIC
产品培训模块: Voltage Supervisor 101
标准包装: 98
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 160 ms
电压 - 阀值: 3.08V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 管件
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
POWER-FAIL COMPARATOR
INPUT
POWER
ADM663A
3.3V
The power-fail comparator is an independent comparator that
can be used to monitor the input power supply. The inverting
R1
V CC
input of the comparator is internally connected to a 1.25 V
reference voltage. The noninverting input is available at the PFI
1.25V
PFI
+
PFO
TO MICROPROCESSOR NMI
input. This input is used to monitor the input power supply via
a resistive divider network. When the voltage on the PFI input
drops below 1.25 V, the comparator output (PFO) goes low,
indicating a power failure. For early warning of power failure,
the comparator is used to monitor the preregulator input simply
by choosing an appropriate resistive divider network. The PFO
output is used to interrupt the processor so that a shutdown
procedure is implemented before the power is lost.
R2
3.3V
PFO
ADM706P/ADM706R/
ADM706S/ADM706T/
ADM708R/ADM708S/
ADM708T
R3
INPUT
POWER
R1
1.25V
PFO
POWER-FAIL
0V
0V V L
V IN
V H
POWER-FAIL
PFI
OUTPUT
Figure 18. Adding Hysteresis to the Power-Fail Comparator
V H = 1 . 25 ? 1 + ? ? R1 ?
? ?
? ?
? R2 × R3 ?
R2
INPUT
ADM706P/ADM706R/
ADM706S/ADM706T/
ADM708R/ADM708S/
ADM708T
? ? R2 + R3 ? ?
? ?
V L = 1 . 25 + R1 ?
? CC
? 1 . 25 ?
Figure 17. Power-Fail Comparator
? 1. 25
? R2
V
?
R3 ?
V MID = 1 . 25 ?
? R1 + R2 ?
ADDING HYSTERESIS TO THE POWER-FAIL
COMPARATOR
For increased noise immunity, hysteresis can be added to the
power-fail comparator. Because the comparator circuit is
noninverting, hysteresis is added simply by connecting a resistor
between the PFO output and the PFI input as shown in Figure 18 .
When PFO is low, Resistor R3 sink s current from the summing
junction at the PFI pin. When PFO is high, Resistor R3 sources
current into the PFI summing junction. This results in differing
trip levels for the comparator. Further noise immunity is achieved
by connecting a capacitor between PFI and GND.
?
? R2 ?
VALID RESET BELOW 1 V V CC
The ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/
ADM708T are guaranteed to provide a valid reset level with V CC
as low as 1 V. Refer to the Typical Performance Characteristics
section. As V CC drops below 1 V, the internal transistor does not
have sufficient drive to hold it on so the voltage on RESET is no
longer held at 0 V. A pull-down resistor, as shown in Figure 19 , can
be connected externally to hold the line low if it is required.
ADM706R/ADM706S/
ADM706T/ADM708R/
ADM708S/ADM708T
RESET
GND
R1
Figure 19. RESET Valid Below 1 V
Rev. C | Page 11 of 16
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