参数资料
型号: ADM709LANZ
厂商: Analog Devices Inc
文件页数: 3/4页
文件大小: 0K
描述: IC SUPERVISOR MPU 4.65V RS 8DIP
标准包装: 50
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.65V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
产品目录页面: 799 (CN2011-ZH PDF)
ADM709
V CC
V TH
ADM709
RESET
GENERATOR
RESET
RESET at Voltages < 1 V
The ADM709 RESET output is guaranteed to operate with
supply voltages as low as 1 V. If it is desired that the RESET
output remains low below 1 V, then a pull-down resistor should
GND
be connected between the RESET output and GND. A resistor
of 100 k ? is suitable. This is illustrated in Figure 5.
Figure 1. Functional Block Diagram
ADM709
RESET
V CC
ADM709
RESET
GND
V CC
μP
RESET
GND
R1
GND
Figure 5. RESET Valid @ V CC < 1 V
Glitch Immunity
Figure 2. Typical Operating Circuit
CIRCUIT INFORMATION
RESET Output
RESET is an active low output which provides a reset signal to
the microprocessor whenever the V CC supply voltage is below
the reset threshold. An internal timer holds RESET low for
140 ms after the voltage on V CC rises above the threshold. This
is intended as a power-on reset signal for the processor. It allows
time for the power supply and microprocessor to stabilize after
power up. Similarly a power supply brownout will initiate a pro-
cessor reset. On power-down, the RESET output remains low
with V CC as low as 1 V. This ensures that the microprocessor is
The ADM709 is immune to short transients which may occur
on the V CC line. This is important so that spurious resets are not
generated as a result of minor glitches on the power supply.
Additional glitch immunity may be obtained by connecting a
capacitor (0.1 μ F or greater) as close as possible to the V CC pin
on the device.
Microprocessors with Bidirectional I-O
Some microprocessors or microcontrollers such as the
MC68HC11 have bidirectional reset lines. In order to avoid
signal contention, a resistor of 4.7 k ? should be connected
between the ADM709 RESET output and the microcontroller
RESET line. This arrangement is shown in Figure 6.
held in a stable shutdown condition as the power supply drops.
+5V
BUFFERED
RESET
V CC
VRT
VRT
V CC
ADM709
μP
RESET
t RS
RESET
GND
RESET
GND
Figure 3. Power Off/On RESET Timing
Figure 6. Interfacing to Microprocessors with
Bidirectional RESET
V CC
RESET
400ms/DIV
Figure 4. RESET Output vs. V CC
REV. 0
–3 –
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