参数资料
型号: ADM800MARN-REEL
厂商: Analog Devices Inc
文件页数: 4/12页
文件大小: 0K
描述: IC SUPERVISOR MPU 4.40V 16SOIC
标准包装: 2,500
类型: 备用电池电路
监视电压数目: 1
输出: 开路漏极,推挽式
复位: 高有效/低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.4V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC N
包装: 带卷 (TR)
ADM691A/ADM693A/ADM800L/M
PIN DESCRIPTIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
V BATT
V OUT
V CC
GND
BATT ON
LOW LINE
OSC IN
OSC SEL
PFI
PFO
WDI
CE OUT
CE IN
WDO
RESET
RESET
Function
Backup Battery Input. Connect to external battery or capacitor. Connect to ground if a backup battery is
not used.
Output Voltage, V CC or V BATT is internally switched to V OUT depending on which is at the highest poten-
tial. When V CC is higher than V BATT and is also higher than the reset threshold, V CC is switched to V OUT .
When V CC is lower than V BATT and below the reset threshold, V BATT is switched to V OUT . Connect V OUT to
V CC if a backup battery is not being used.
Power Supply Input; +5 V.
0 V. Ground reference for all signals.
Logic Output. BATT ON goes high when V OUT is internally switched to the V BATT input. It goes low when
V OUT is internally switched to V CC . The output may also be used to drive the base (via a resistor) of an ex-
ternal PNP transistor to increase the output current above the 250 mA rating of V OUT .
Logic Output. LOW LINE goes low when V CC falls below the reset threshold. It returns high as soon as
V CC rises above the reset threshold.
Oscillator Logic Input. With OSC SEL high or floating, the internal oscillator is enabled and sets the reset
delay and the watchdog timeout period. Connecting OSC IN low selects 100 ms while leaving it floating
selects 1.6 sec. With OSC SEL low, OSC IN can be driven by an external clock signal or an external ca-
pacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the
watchdog timeout period. (See Table II and Figure 4.)
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscil-
lator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator
input, OSC IN, is enabled. OSC SEL has a 10 μ A internal pullup.
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than
1.25 V, PFO goes low. Connect PFI to GND or V OUT when not used.
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than
1.25 V.
Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watch-
dog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition on the
WDI line. The Watchdog Timer may be disabled if WDI is left floating or is driven to midsupply.
Output. CE OUT goes low only when CE IN is low and V CC is above the reset threshold. If CE IN is low when
reset is asserted, CE OUT will remain low for 15 μ s or until CE IN goes high, whichever occurs first.
Chip Enable Input. The input to the CE gating circuit. Connect to GND or V OUT if not used.
Logic Output. The Watchdog Output, WDO , goes low if WDI remains either high or low for longer than
the Watchdog timeout period. WDO is set high by the next transition at WDI. WDO remains high if WDI
is unconnected.
Logic Output. RESET goes low if V CC falls below the Reset Threshold. It remains low for 200 ms typ after
V CC goes above the reset threshold.
Logic Output. RESET is an open-drain output. It is the inverse of RESET .
PIN CONFIGURATIONS
V BATT
V OUT
1
2
16 RESET
15 RESET
CE IN
V CC
GND
BATT ON
LOW LINE
3
4
5
6
ADM691A
ADM693A
ADM800L
ADM800M
TOP VIEW
14 WDO
13
12 CE OUT
11 WDI
OSC IN
7 (Not to Scale) 10 PFO
OSC SEL
8
–4 –
9
PFI
REV. 0
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