参数资料
型号: ADM809MAKS-REEL7
厂商: Analog Devices Inc
文件页数: 8/12页
文件大小: 0K
描述: IC SUPERVISOR P/P 4.38V SC70-3
标准包装: 3,000
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.38V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SC-70,SOT-323
供应商设备封装: SC-70-3
包装: 带卷 (TR)

ADM803/ADM809/ADM810
INTERFACING TO OTHER DEVICES
The ADM803/ADM809/ADM810 series is designed to integrate
with as many devices as possible and, therefore, has a standard
output dependent on V CC . This enables the parts to be used in
both 3 V and 5 V, or any nominal voltage within the minimum
and maximum specifications for V CC . This design simplifies
interfacing the ADM803/ADM809/ADM810 to other devices.
ENSURING A VALID RESET OUTPUT DOWN TO
V CC = 0 V
When V CC falls below 0.8 V, the ADM803/ADM809 RESET no
longer sinks c urrent. A high impedance CMOS logic input
connected to RESET may, therefore, drift to undetermined logic
levels. To eliminate this problem, a 100 kΩ resistor should be
connected from RESET to ground.
V CC
ADM803/ADM809/ADM810, the possibility of a malfunction
during a power failure is greatly reduced because the devices
can operate effectively even when there are large degradations
of the supply voltages. Another advantage is the very accurate
internal voltage reference circuit of the ADM803/ADM809/
ADM810. These benefits combine to produce an exceptionally
reliable voltage monitor circuit.
INTERFACING TO MICROPROCESSORS WITH
MULTIPLE INTERRUPTS
In a number of cases, it is necessary to interface many interrupts
from different devices (for example, thermal, altitude, and
velocity sensors). The ADM803/ADM809/ADM810 can easily
be integrated into existing interrupt-handling circuits, as shown
in Figure 13, or can be used as standalone devices.
V CC
ADM809
V CC
PRIORITY ENCODER
74LS147
4-LINE BCD TO
MICROPROCESSOR
RESET
V CC
ADM809
GND
RESET
OTHER SENSING
DEVICES
Figure 12. Ensuring a Valid Reset Output Down to V CC = 0 V
GND
BENEFITS OF AN ACCURATE RESET THRESHOLD
In other microprocessors, tolerances in supply voltages lead
to an overall increase in reset tolerance levels due to the
deterioration of the reset circuit’s power supply. In the
Rev. H | Page 8 of 12
Figure 13. Interfacing to Microprocessors with Multiple Interrupts
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