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参数资料
| 型号： | ADM825ZYKSZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR W/RESET SC70-5 |
| 标准包装： | 1 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 推挽式，推挽式 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 140 ms |
| 电压 - 阀值： | 2.32V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-TSSOP（5 引线），SC-88A，SOT-353 |
| 供应商设备封装： | SC-70-5 |
| 包装： | 标准包装 |
| 其它名称： | ADM825ZYKSZ-R7DKR |
Data Sheet
CIRCUIT DESCRIPTION
The ADM823/ADM824/ADM825 provide microprocessor
supply voltage supervision by controlling the reset input of the
microprocessor. Code execution errors are avoided during
power-up, power-down, and brownout conditions by asserting a
reset signal when the supply voltage is below a preset threshold.
Errors are also avoided by allowing supply voltage stabilization
with a fixed timeout reset pulse after the supply voltage rises
above the threshold. In addition, problems with microprocessor
code execution can be monitored and corrected with a watchdog
timer (ADM823/ADM824). By including watchdog strobe
instructions in microprocessor code, a watchdog timer can
detect whether the microprocessor code breaks down or becomes
stuck in an infinite loop. If this happens, the watchdog timer
asserts a reset pulse that restarts the microprocessor in a known
state. If the user detects a problem with the system’s operation, a
manual reset input is available (ADM823/ADM825) to reset the
microprocessor with an external push-button, for example.
RESET OUTPUT
The ADM823 features an active low, push-pull reset output, and
the ADM824/ADM825 feature dual active low and active high
push-pull reset outputs. For active low and active high outputs,
the reset signal is guaranteed to be logic low and logic high,
respectively, for V CC ≥ 1 V.
The reset output is asserted when V CC is below the reset
threshold (V TH ), when MR is driven low, or when WDI is not
serviced within the watchdog timeout period (t WD ). Reset
remains asserted for the duration of the reset active timeout
period (t RP ) after V CC rises above the reset threshold, after MR
transitions from low to high, or after the watchdog timer times
out. Figure 15 illustrates the behavior of the reset outputs.
ADM823/ADM824/ADM825
MANUAL RESET INPUT
The ADM823/ADM825 feature a manual reset input (MR)
which, when driven low, asserts the reset output. When MR
transitions from low to high, reset remains asserted for the
duration of the reset active timeout period before deasserting.
The MR input has a 52 kΩ internal pull-up so that the input is
always high when unconnected. An external push-button
switch can be connected between MR and ground so that the
user can generate a reset. Debounce circuitry for this purpose is
integrated on chip. Noise immunity is provided on the MR
input and fast, negative-going transients o f u p to 100 ns (typical)
are ignored. A 0.1 μF capacitor between MR and ground
provides additional noise immunity.
WATCHDOG INPUT
The ADM823/ADM824 feature a watchdog timer that monitors
microprocessor activity. A timer circuit is cleared with every
low-to-high or high-to-low logic transition on the watchdog
input pin (WDI), which detects pulses as short as 50 ns. If the
timer counts through the preset watchdog timeout period (t WD ),
reset is asserted. The microprocessor is required to toggle the
WDI pin to avoid being reset. Failure of the microprocessor to
toggle WDI within the timeout period, therefore, indicates a
code execution error, and the reset pulse generated restarts the
microprocessor in a known state.
In addition to logic transitions on WDI, the watchdog timer is
also cleared by a reset assertion due to an undervoltage condi-
tion on V CC or by MR being pulled low. When reset is asserted,
the watchdog timer is cleared and does not begin counting again
until reset is deasserted. The watchdog timer can be disabled by
leaving WDI floating or by three-stating the WDI driver.
V CC
V CC
1V
0V
V TH
V TH
V CC
V CC
1V
0V
V TH
RESET
V CC
t RP
t RD
RESET
V CC
t RP
t WD
t RP
0V
0V
t RD
RESET
V CC
1V
0V
t RP
Figure 15. Reset Timing Diagram
WDI
V CC
0V
Figure 16. Watchdog Timing Diagram
Rev. D | Page 9 of 12
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