参数资料
型号: ADM8696ARW
厂商: Analog Devices Inc
文件页数: 5/13页
文件大小: 0K
描述: IC SUPERVSR MPU ADJ/RESET 16SOIC
标准包装: 47
类型: 备用电池电路
监视电压数目: 1
输出: 推挽式,推挽式
复位: 高有效/低有效
复位超时: 最小为 35 ms
电压 - 阀值: 1.3V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 管件
ADM8696/ADM8697
CIRCUIT INFORMATION
Battery Switchover Section (ADM8696)
The battery switchover circuit is designed to switch over to
battery backup in the event of a power failure. When LL IN
is below the reset threshold and V CC is below V BATT , then
V BATT is switched to V OUT .
During normal operation, with V CC higher than V BATT , V CC is
internally switched to V OUT via an internal PMOS transistor
switch. This switch has a typical on resistance of 0.7 ? and can
supply up to 100 mA at the V OUT terminal. V OUT is normally
used to drive a RAM memory bank which may require instanta-
neous currents of greater than 100 mA. If this is the case, then
a bypass capacitor should be connected to V OUT . The capacitor
will provide the peak current transients to the RAM. A capaci-
tance value of 0.1 μ F or greater may be used.
If the continuous output current requirement at V OUT exceeds
100 mA or if a lower V CC –V OUT voltage differential is desired,
Low Line RESET OUTPUT
RESET is an active low output that provides a RESET signal to
the microprocessor whenever the Low Line Input (LL IN ) is be-
low 1.3 V. The LL IN input is normally used to monitor the
power supply voltage. An internal timer holds RESET low for
50 ms after the voltage on LL IN rises above 1.3 V. This is in-
tended as a power-on RESET signal for the processor. It allows
time for the power supply and microprocessor to stabilize. On
power-down, the RESET output remains low, with V CC as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition.
The LL IN comparator has approximately 12 mV of hysteresis
for enhanced noise immunity.
In addition to RESET , an active high RESET output is also
available. This is the complement of RESET and is useful for
processors requiring an active high RESET.
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output can directly
drive the base of the external transistor.
A 7 ? MOSFET switch connects the V BATT input to V OUT dur-
ing battery backup. This MOSFET has very low input-to-out-
LL IN
RESET
V2
t 1
V1
V2
t 1
V1
put differential (dropout voltage) at the low current levels
required for battery backup of CMOS RAM or other low power
CMOS circuitry. The supply current in battery backup is typi-
cally 0.4 μ A.
The ADM8696 operates with battery voltages from 2.0 V to
V CC –0.3 V). High value capacitors, either standard electrolytic
or the farad-size double layer capacitors, can also be used for
short-term memory backup. A small charging current of typi-
cally 10 nA (0.1 μ A max) flows out of the V BATT terminal. This
current is useful for maintaining rechargeable batteries in a fully
charged condition. This extends the life of the backup battery
by compensating for its self-discharge current. Also note that
this current poses no problem when lithium batteries are used
for backup since the maximum charging current (0.1 μ A) is safe
for even the smallest lithium cells.
If the battery switchover section is not used, V BATT should be
connected to GND and V OUT should be connected to V CC .
LOW LINE
t 1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 2. Power-Fail Reset Timing
Watchdog Timer RESET
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within
the selected timeout period, a RESET pulse is generated. The
ADM8696/ADM8697 may be configured for either a fixed
“short” 100 ms or a “long” 1.6 second timeout period or for an
adjustable timeout period. If the “short” period is selected,
some systems may be unable to service the watchdog timer im-
mediately after a reset, so a “long” timeout is automatically ini-
V CC
V BATT
GATE DRIVE
V OUT
tiated directly after a reset is issued. The watchdog timer is
restarted at the end of Reset, whether the Reset was caused by
lack of activity on WDI or by LL IN falling below the reset
threshold.
The normal (short) timeout period becomes effective following
700
mV
100
mV
INTERNAL
SHUTDOWN SIGNAL
WHEN
V BATT > (V CC + 0.7V)
BATT ON
(ADM8691, ADM8693,
ADM8695, ADM8696)
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is-
sued after each timeout period (1.6 s). The watchdog monitor
can be deactivated by floating the Watchdog Input (WDI) or by
REV. A
Figure 1. Battery Switchover Schematic
–5 –
connecting it to midsupply.
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