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参数资料
| 型号： | ADM8697ARW |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 电源管理 |
| 英文描述： | bqTINY-II Dual Input USB/AC Adpater 1-Cell Li-Ion Charger w/Charge Enable & AC Present, No Taper 10-SON -40 to 85 |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16 |
| 封装： | MS-013AA, SOIC-16 |
| 文件页数： | 6/12页 |
| 文件大小： | 195K |
| 代理商： | ADM8697ARW |
ADM8696/ADM8697
REV. 0
–6–
T able I. ADM8696, ADM8697 Reset Pulse Width and Watchdog T imeout Selections
Watchdog T imeout Period
Immediately After Reset
Reset Active Period
OSC SE L
OSC IN
Normal
Low
Low
Floating or High
Floating or High
External Clock Input
External Capacitor
Low
Floating or High
1024 CLK S
400 ms
×
C/47 pF
100 ms
1.6 s
4096 CLK S
1.6 s
×
C/47 pF
1.6 s
1.6 s
512 CLK S
200 ms
×
C/47 pF
50 ms
50 ms
NOT E
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. T he nominal
internal oscillator frequency is 10.24 kHz. T he nominal oscillator frequency with external capacitor is: F
OSC
(Hz) = 184,000/C (pF).
WDI
t
1
= RESET TIME
t
2
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t
3
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
t
1
WDO
RESET
t
2
t
3
t
1
t
1
Figure 3. Watchdog Timeout Period and Reset Active Time
T he watchdog timeout period defaults to 1.6 s and the reset
pulse width defaults to 50 ms, but these times to be adjusted as
shown in T able I. Figure 4 shows the various oscillator configu-
rations that can be used to adjust the reset pulse width and
watchdog timeout period.
T he internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. In either case, immedi-
ately after a reset the timeout period is 1.6 s. T his gives the mi-
croprocessor time to reinitialize the system. If OSC IN is low,
the 100 ms watchdog period becomes effective after the first
transition of WDI. T he software should be written such that the
I/O port driving WDI is left in its power-up reset state until the
initialization routines are completed and the microprocessor is
able to toggle WDI at the minimum watchdog timeout period of
70 ms.
OSC IN
OSC SEL
ADM869x
CLOCK
0 TO 500kHz
7
8
Figure 4a. External Clock Source
C
OSC
OSC IN
OSC SEL
ADM869x
7
8
Figure 4b. External Capacitor
NC
NC
OSC IN
OSC SEL
ADM869x
7
8
Figure 4c. Internal Oscillator (1.6 s Watchdog)
NC
OSC IN
OSC SEL
ADM869x
7
8
Figure 4d. Internal Oscillator (100 ms Watchdog)
Watchdog Output (
WDO
)
T he Watchdog Output
WDO
provides a status output that goes
low if the watchdog timer “times out” and remains low until set
high by the next transition on the watchdog input.
WDO
is also
set high when LL
IN
goes below the reset threshold.
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