参数资料
| 型号： | ADM8830ARUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/8页 |
| 文件大小： | 0K |
| 描述： | IC CHARGE PUMP REG TFT 20TSSOP |
| 标准包装： | 75 |
| 应用： | 转换器，TFT，LCD |
| 输入电压： | 2.6 V ~ 3.6 V |
| 输出数： | 3 |
| 输出电压： | -10.2V，5.1V，15.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
ADM8830
PIN CONFIGURATIONS
C1– 1
C1+ 2
V CC 3
TSSOP
20 GND
19 –10VOUT
18 C4+
LFCSP
VOUT 4
LDO_IN 5
+5VOUT 6
+5VIN 7
ADM8830
TOP VIEW
(NOT TO SCALE)
17 C4–
16 C2+
15 C2–
14 C3+
V CC 1
VOUT 2
LDO_IN 3
+5VOUT 4
+5VIN 5
PIN 1
INDICATOR
ADM8830
TOP VIEW
15 C4–
14 C2+
13 C2–
12 C3+
11 C3–
LDO_ON/ OFF 8
SHDN 9
SCAN/ BLANK 10
13 C3–
12 +15VOUT
11 CLKIN
PIN FUNCTION DESCRIPTIONS
PIN NUMBER
TSSOP
1, 2
3
4
5
6
7
8
9
10
11
12
13, 14
15, 16
17, 18
19
20
LFCSP
19, 20
1
2
3
4
5
6
7
8
9
10
11, 12
13, 14
15, 16
17
18
MNEMONIC
C1–, C1+
V CC
VOUT
LDO_IN
+5VOUT
+5VIN
LDO_ON/ OFF
SHDN
SCAN/ BLANK
CLKIN
+15VOUT
C3–, C3+
C2–, C2+
C4–, C4+
–10VOUT
GND
FUNCTION
EXTERNAL CAPACITOR C1 IS CONNECTED BETWEEN THESE PINS. A 2.2 μF CAPACITOR IS RECOMMENDED.
POSITIVE SUPPLY VOLTAGE INPUT. CONNECT THIS PIN TO 3 V SUPPLY WITH A 2.2 μF DECOUPLING CAPACITOR.
VOLTAGE DOUBLER OUTPUT. THIS IS DERIVED BY DOUBLING THE 3 V SUPPLY. A 2.2 μF CAPACITOR TO
GROUND IS REQUIRED ON THIS PIN.
VOLTAGE REGULATOR INPUT. THE USER HAS THE OPTION TO BYPASS THIS CIRCUIT USING THE
LDO_ON/ OFF PIN.
+5.1 V OUTPUT PIN. THIS IS DERIVED BY DOUBLING AND REGULATING THE 3 V SUPPLY. A 2.2 μF CA-
PACITOR TO GROUND IS REQUIRED ON THIS PIN TO STABILIZE THE REGULATOR.
+5.1 V INPUT PIN. THIS IS THE INPUT TO THE VOLTAGE TRIPLER AND DOUBLER INVERTER CHARGE PUMP
CIRCUITS.
CONTROL LOGIC INPUT. 3 V CMOS LOGIC. A LOGIC HIGH SELECTS THE INTERNAL LDO FOR REGULATION OF
THE 5 V VOLTAGE DOUBLER OUTPUT. A LOGIC LOW ISOLATES THE INTERNAL LDO FROM THE REST OF THE CHARGE
PUMP CIRCUITS. THIS ALLOWS THE USE OF AN EXTERNAL LDO TO REGULATE THE 5 V VOLTAGE DOUBLER
OUTPUT. THE OUTPUT OF THIS LDO IS THEN FED BACK INTO THE VOLTAGE TRIPLER AND DOUBLER/INVERTER
CIRCUITS OF THE ADM8830.
DIGITAL INPUT. 3 V CMOS LOGIC. ACTIVE LOW SHUTDOWN CONTROL. THIS SHUTS DOWN THE TIMING
GENERATOR AND ENABLES THE DISCHARGE CIRCUIT TO DISSIPATE THE CHARGE ON THE VOLTAGE OUTPUTS,
THUS DRIVING THEM TO 0 V.
DRIVE MODE INPUT. 3 V CMOS LOGIC. A LOGIC HIGH PLACES THE PART IN SCAN (HIGH CURRENT) MODE
AND THE CHARGE PUMP IS DRIVEN BY THE INTERNAL OSCILLATOR. A LOGIC LOW PLACES THE PART IN BLANKING
(LOW CURRENT) MODE AND THE CHARGE PUMP IS DRIVEN BY THE (SLOWER) EXTERNAL OSCILLATOR. THIS IS
A POWER SAVING FEATURE ON THE ADM8830.
EXTERNAL CLOCK INPUT. DURING A BLANKING PERIOD, THE OSCILLATOR CIRCUIT SELECTS THIS PIN TO DRIVE
THE CHARGE PUMP CIRCUIT. THIS IS AT A LOWER FREQUENCY THAN THE INTERNAL OSCILLATOR, RESULTING IN
LOWER QUIESCENT CURRENT CONSUMPTION, THUS SAVING POWER.
+15.3 V OUTPUT PIN. THIS IS DERIVED BY TRIPLING THE +5.1 V REGULATED OUTPUT. A 1 μF CAPACITOR
IS REQUIRED ON THIS PIN.
EXTERNAL CAPACITOR C3 IS CONNECTED BETWEEN THESE PINS. A 1 μF CAPACITOR IS RECOMMENDED.
EXTERNAL CAPACITOR C2 IS CONNECTED BETWEEN THESE PINS. A 1 μF CAPACITOR IS RECOMMENDED.
EXTERNAL CAPACITOR C4 IS CONNECTED BETWEEN THESE PINS. A 1 μF CAPACITOR IS RECOMMENDED.
–10.2 V OUTPUT PIN. THIS IS DERIVED BY DOUBLING AND INVERTING THE +5.1 V REGULATED OUTPUT.
A 1 μF CAPACITOR IS REQUIRED ON THIS PIN.
DEVICE GROUND PIN.
–4–
REV. B
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