参数资料
型号: ADM8832EB-EVALZ
厂商: Analog Devices Inc
文件页数: 6/12页
文件大小: 0K
描述: BOARD EVALUATION ADM8832 REG
标准包装: 1
主要目的: 特殊用途 DC/DC,LCD 电源
输出及类型: 3,非隔离
输出电压: 5.1V,15.3V,-10.2V
电流 - 输出: 5mA,1µA,1µA
输入电压: 2.6 ~ 3.6V
稳压器拓扑结构: 升压
频率 - 开关: 100kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ADM8832
相关产品: ADM8832ACPZ-ND - IC CHARGE PUMP REG TFT 20LFCSP
ADM8832ACPZ-REEL7-ND - IC CHARGE PUMP REG TFT 20LFCSP
ADM8832ACPZ-REEL-ND - IC CHARGE PUMP REG TFT 20LFCSP

ADM8832
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V CC
VOUT
LDO_IN
+5VOUT
+5VIN
1
2
3
4
5
PIN 1
INDICATOR
ADM8832
TOP VIEW
15 C4–
14 C2+
13 C2–
12 C3+
11 C3–
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11, 12
13, 14
15, 16
17
18
19, 20
Mnemonic
V CC
VOUT
LDO_IN
+5VOUT
+5VIN
LDO_ON/OFF
SHDN
SCAN/BLANK
CLKIN
+15VOUT
C3?, C3+
C2?, C2+
C4?, C4+
?10VOUT
GND
C1?, C1+
Function
Positive Supply Voltage Input. Connect this pin to 3 V supply with a 2.2 μF decoupling capacitor.
Voltage Doubler Output. This is derived by doubling the 3 V supply. A 2.2 μF capacitor to ground is required on
this pin.
Voltage Regulator Input. The user has the option to bypass this circuit using the LDO_ON/OFF pin.
+5.1 V Output Pin. This is derived by doubling and regulating the +3 V supply. A 2.2 μF capacitor to ground is
required on this pin to stabilize the regulator.
+5.1 V Input Pin. This is the input to the voltage tripler and doubler inverter charge pump circuits.
Control Logic Input. 3 V CMOS logic. A logic high selects the internal LDO for regulation of the 5 V voltage
doubler output. A logic low isolates the internal LDO from the rest of the charge pump circuits. This allows the
use of an external LDO to regulate the 5 V voltage doubler output. The output of this LDO is then fed back into
the voltage tripler and doubler/inverter circuits of the ADM8832.
Digital Input. 3 V CMOS logic. Active low shutdown control. This pin shuts down the timing generator and
enables the discharge circuit to dissipate the charge on the voltage outputs, thus driving them to 0 V.
Drive Mode Input. 3 V CMOS logic. A logic high places the part in scan (high current) mode, and the charge
pump is driven by the internal oscillator. A logic low places the part in blanking (low current) mode, and the
charge pump is driven by the (slower) external oscillator. This is a power saving feature on the ADM8832.
External CLOCK Input. During a blanking period, the oscillator circuit selects this pin to drive the charge pump
circuit. This is at a lower frequency than the internal oscillator, resulting in lower quiescent current
consumption, thus saving power.
+15.3 V Output Pin. This is derived by tripling the +5.1 V regulated output. A 1 μF capacitor is required on
this pin.
External capacitor C3 is connected between these pins. A 1 μF capacitor is recommended.
External capacitor C2 is connected between these pins. A 1 μF capacitor is recommended.
External capacitor C4 is connected between these pins. A 1 μF capacitor is recommended.
?10.2 V Output Pin. This is derived by doubling and inverting the +5.1 V regulated output. A 1 μF capacitor is
required on this pin.
Device Ground Pin.
External capacitor C1 is connected between these pins. A 2.2 μF capacitor is recommended.
Rev. A | Page 6 of 12
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