参数资料
| 型号： | ADM9690ARNZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/6页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR PS/WATCHDOG 8SOIC |
| 标准包装： | 98 |
| 类型： | 监视器电路 |
| 监视电压数目： | 1 |
| 输出： | 推挽式，图腾柱 |
| 复位： | 低有效 |
| 复位超时： | 标准为 10 ms、50 ms |
| 电压 - 阀值： | 4.31V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
ADM9690
POWER SUPPLY AND WATCHDOG MONITORING
CIRCUIT
The ADM9690 contains a power supply voltage monitoring
comparator and a watchdog timer monitor. Either V MON drop-
ping outside tolerance or the watchdog timer timing out results
in a reset sequence as discussed below. Two reset outputs are
provided. RESET(1) and RESET(2).
POWER FAIL/POWER-ON RESET
When V MON falls below the reset threshold (4.4 V) both RESET
outputs are forced low immediately.
On power-up, RESET(1) will remain low for 50 milliseconds
after V MON rises above the reset threshold. This provides a
power-on reset for the microprocessor. RESET(2) remains
active low for an additional 10 ms. RESET(1) is intended to
V CC
provide a power-on reset signal for the μ P while RESET(2) is
used to hold additional circuitry in a reset state until the μ P has
regained control following a power-up.
The guaranteed minimum and maximum thresholds for the
ADM9690 are 4.3 V and 4.5 V.
Watchdog Timer RESET
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an infinite
loop. An output line on the processor may be used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, both RESET outputs are taken active
(low). RESET(1) remains low for 50 ms and RESET(2) re-
mains low for an additional 10 ms . Each transition (either
positive-going or negative-going) of WDI after RESET(1) has
gone inactive restarts the watchdog timer. The actual watchdog
timeout period is adjustable using SEL1 and SEL2. Four timeout
periods are selectable. Please refer to Table I.
V MON
4.31V
ADM9690
The watchdog timer is restarted at the end of RESET(1)
(RESET(1) going high), whether the reset was caused by lack of
OSC SEL1
OSC SEL2
WATCHDOG
TIMEBASE
RESET(1)
TIMER
RESET(2)
TIMER
RESET(1)
RESET(2)
activity on WDI or by V MON falling below the reset threshold.
Table I.
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION
DETECTOR
SEL2
0
SEL1
0
Watchdog Timeout
Period t WD (ms)
0.75
GND
Figure 6. Functional Block Diagram
V MON
0
1
1
WDI
1
0
1
t WD
1.5
12.5
25
REV. A
t 1
RESET(1)
t 2
RESET(2)
Figure 7. Power-On RESET Timing
– 5 –
RESET(1)
RESET(2)
t 1
t 2
Figure 8. Watchdog RESET Timing
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