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| 型号： | ADN2807ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 48LFCSP |
| 标准包装： | 2,500 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STM |
| 输入： | CML |
| 输出： | CML |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 622MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP |
| 包装： | 带卷 (TR) |
ADN2807
Rev. A | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
TOP VIEW
ADN2807
THRADJ 1
VCC 2
VEE 3
VREF 4
PIN 5
NIN 6
SLICEP 7
SLICEN 8
VEE 9
LOL 10
XO1 11
XO2 12
RE
FCLKN
1
3
REFCLKP
14
R
E
FSEL
15
VEE
16
TDINP
17
TDINN
1
8
VEE
19
V
CC
2
0
C
F
1
21
VEE
22
R
E
FSEL1
23
R
E
FSEL0
24
36 VCC
35 VCC
34 VEE
33 VEE
32 SEL0
31 NC
30 SEL1
29 VEE
28 VCC
27 VEE
26 VCC
25 CF2
48
LOOPEN
47
VC
C
46
VEE
45
SD
OU
T
44
B
Y
PA
SS
43
VEE
42
VEE
4
1
CLK
O
UTP
4
0
CLK
O
UTN
39
SQ
U
E
LC
H
3
8
DATAOUTP
3
7
DATAOUTN
03877-0-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
THRADJ
AI
LOS Threshold Setting Resistor.
2, 26, 28, Pad
VCC
P
Analog Supply.
3, 9, 16, 19,
22, 27, 29, 33,
34, 42, 43, 46
VEE
P
Ground.
4
VREF
AO
Internal VREF Voltage. Decouple to GND with a 0.1 F capacitor.
5
PIN
AI
Differential Data Input.
6
NIN
AI
Differential Data Input.
7
SLICEP
AI
Differential Slice Level Adjust Input.
8
SLICEN
AI
Differential Slice Level Adjust Input.
10
LOL
DO
Loss-of-Lock Indicator. LVTTL active high.
11
XO1
AO
Crystal Oscillator.
12
XO2
AO
Crystal Oscillator.
13
REFCLKN
DI
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
14
REFCLKP
DI
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
15
REFSEL
DI
Reference Source Select. 0 = on-chip oscillator with external crystal. 1 = external clock source, LVTTL.
17
TDINP
AI
Differential Test Data Input. CML.
18
TDINN
AI
Differential Test Data Input. CML.
20, 47
VCC
P
Digital Supply.
21
CF1
AO
Frequency Loop Capacitor.
23
REFSEL1
DI
Reference Frequency Select (See Table 6) LVTTL.
24
REFSEL0
DI
Reference Frequency Select (See Table 6) LVTTL.
25
CF2
AO
Frequency Loop Capacitor.
30
SEL1
DI
Data Rate Select (See Table 5) LVTTL.
31
NC
No Connect.
32
SEL0
DI
Data Rate Select (See Table 5) LVTTL.
35, 36
VCC
P
Output Driver Supply.
37
DATAOUTN
DO
Differential Retimed Data Output. CML.
38
DATAOUTP
DO
Differential Retimed Data Output. CML.
39
SQUELCH
DI
Disable Clock and Data Outputs. Active high. LVTTL.
40
CLKOUTN
DO
Differential Recovered Clock Output. CML.
41
CLKOUTP
DO
Differential Recovered Clock Output. CML.
44
BYPASS
DI
Bypass CDR Mode. Active high. LVTTL.
45
SDOUT
DO
Loss-of-Signal Detect Output. Active high. LVTTL.
48
LOOPEN
DI
Enable Test Data Inputs. Active high. LVTTL.
1Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output
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