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参数资料
| 型号： | ADN2815ACPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/24页 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA REC 1.25GBPS 32LFCSP |
| 标准包装： | 1,500 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | CML |
| 输出： | LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.25GHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 带卷 (TR) |
Data Sheet
ADN2815
Rev. C | Page 15 of 24
The CTRLB[7] bit defaults to 0. In this mode, the LOL pin
operates in the normal operating mode, that is, it is asserted
only when the ADN2815 is in acquisition mode and deasserts
when the ADN2815 has reacquired lock.
HARMONIC DETECTOR
The ADN2815 provides a harmonic detector, which detects
whether or not the input data has changed to a lower harmonic
of the data rate that the VCO is currently locked onto. For
example, if the input data instantaneously changes from OC-12,
622.08Mb/s to an OC-3, 155.52 Mb/s bit stream, this could be
perceived as a valid OC-12 bit stream, because the OC-3 data
pattern is exactly 4× slower than the OC-12 pattern. Therefore,
if the change in data rate is instantaneous, a 101 pattern at OC-3
would be perceived by the ADN2815 as a 111100001111 pattern
at OC-12. If the change to a lower harmonic is instantaneous, a
typical CDR could remain locked at the higher data rate.
The ADN2815 implements a harmonic detector that automati-
cally identifies whether or not the input data has switched to a
lower harmonic of the data rate that the VCO is currently
locked onto. When a harmonic is identified, the LOL pin is
asserted and a new frequency acquisition is initiated. The
ADN2815 automatically locks onto the new data rate, and the
LOL pin is deasserted.
However, the harmonic detector does not detect higher
harmonics of the data rate. If the input data rate switches to a
higher harmonic of the data rate, then the VCO is currently
locked onto, the VCO loses lock, the LOL pin is asserted, and a
new frequency acquisition is initiated. The ADN2815
automatically locks onto the new data rate.
The time to detect lock to harmonic is
216 × (Td/ρ)
where:
1/Td is the new data rate. For example, if the data rate is
switched from OC-12 to OC-3, then Td = 1/155.52 MHz.
ρ is the data transition density. Most coding schemes seek to
ensure that ρ = 0.5, for example, PRBS, 8B/10B.
When the ADN2815 is placed in lock to reference mode, the
harmonic detector is disabled.
SQUELCH MODE
Two SQUELCH modes are available with the ADN2815.
SQUELCH DATAOUT and CLKOUT mode is selected when
CTRLC[1] = 0 (default mode). In this mode, when the
SQUELCH input, Pin 27, is driven to a TTL high state, both the
clock and data outputs are set to the zero state to suppress
downstream processing. If the SQUELCH function is not
required, Pin 27 should be tied to VEE.
SQUELCH DATAOUT or CLKOUT mode is selected when
CTRLC[1] is 1. In this mode, when the SQUELCH input is
driven to a high state, the DATAOUTN/DATAOUTP pins are
squelched. When the SQUELCH input is driven to a low state,
the CLKOUT pins are squelched. This is especially useful in
repeater applications, where the recovered clock may not be
needed.
I2C INTERFACE
driving multiple peripherals. Two inputs, serial data (SDA) and
serial clock (SCK), carry information between any devices
connected to the bus. Each slave device is recognized by a
unique address. The ADN2815 has two possible 7-bit slave
addresses for both read and write operations. The MSB of the
7-bit slave address is factory programmed to 1. B5 of the slave
address is set by Pin 19, SADDR5. Slave Address Bits [4:0] are
defaulted to all 0s. The slave address consists of the 7 MSBs of
an 8-bit word. The LSB of the word either sets a read or write
operation (see Figure 6). Logic 1 corresponds to a read
operation, while Logic 0 corresponds to a write operation.
To control the device on the bus, the following protocol must be
followed. First, the master initiates a data transfer by establish-
ing a start condition, defined by a high-to-low transition on
SDA while SCK remains high. This indicates that an address/
data stream follows. All peripherals respond to the start
condition and shift the next eight bits (the 7-bit address and the
R/W bit). The bits are transferred from MSB to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCK lines
waiting for the start condition and correct transmitted address.
The R/W bit determines the direction of the data. Logic 0 on the
LSB of the first byte means that the master writes information to
the peripheral. Logic 1 on the LSB of the first byte means that
the master reads information from the peripheral.
The ADN2815 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses, plus the R/W bit. The ADN2815 has eight subaddresses
to enable the user-accessible internal registers (see Table 6
through Table 10). It, therefore, interprets the first byte as the
device address and the second byte as the starting subaddress.
Autoincrement mode is supported, allowing data to be read
from or written to the starting subaddress and each subsequent
address without manually addressing the subsequent
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all registers.
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