参数资料
型号: ADN2817ACPZ-RL7
厂商: Analog Devices Inc
文件页数: 23/40页
文件大小: 0K
描述: IC CLOCK/DATA RECOVERY 32-LFCSP
标准包装: 1,500
类型: 时钟和数据恢复(CDR),多路复用器
PLL:
主要目的: SONET/SDH
输入: CML
输出: CML
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 是/是
频率 - 最大: 2.7GHz
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘,CSP
供应商设备封装: 32-LFCSP-VQ(5x5)
包装: 带卷 (TR)
Data Sheet
ADN2817/ADN2818
Rev. E | Page 3 of 40
REVISION HISTORY
1/13 Rev. D to Rev. E
Moved Revision History Section.....................................................3
Change to Table 8............................................................................15
Changes to Table 15 ........................................................................17
Changes to Rate Selectivity Section ..............................................28
1/12—Rev. C to Rev. D
Changes to Figure 14 ......................................................................12
Updated Outline Dimensions........................................................37
3/10—Rev. B to Rev. C
Changes to Features Section and Applications Section ...............1
Changes to Thermal Resistance Section ........................................9
Added Table 6; Renumbered Sequentially.....................................9
Changes to Table 7 ..........................................................................10
Changes to Table 8 ..........................................................................14
Changes to Table 14 ........................................................................15
Deleted Table 16; Renumbered Sequentially...............................16
Changes to Table 16 ........................................................................16
Changes to I2C Interface Section...................................................24
Changed fREF Ratio to DIV_FREF Ratio.......................................25
Changes to Initiate Frequency Acquisition, Rate Selectivity,
Double Data Rate Mode, and PRBS Generator/Detector
Sections.............................................................................................27
Changes to Table 19 ........................................................................32
Changes to Table 20 ........................................................................34
2/09—Rev. A to Rev. B
Updated Outline Dimensions........................................................37
Changes to Ordering Guide...........................................................37
8/08—Rev. 0 to Rev. A
Changes to Features Section, General Description Section, and
Figure 1...............................................................................................1
Added Bit Rate Monitor Specifications Section and Table 4;
Renumbered Sequentially ................................................................7
Changes to Figure 5 and Table 6 ...................................................10
Changes to Table 7 and Table 8 .....................................................14
Changes to Table 14 ........................................................................15
Added Table 15................................................................................15
Added Table 16................................................................................16
Added Sample Phase Adjust Section and Bit Error Rate (BER)
Monitor Section...............................................................................23
Added Figure 32; Renumbered Sequentially...............................24
Changes to Figure 36 ......................................................................29
Added Exposed Pad Notation to Outline Dimensions..............37
7/07—Revision 0: Initial Version
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