参数资料
型号: ADN4663BRZ
厂商: Analog Devices Inc
文件页数: 7/12页
文件大小: 0K
描述: IC DRIVER DIFF LVDS 2CH 8SOIC
标准包装: 98
类型: 驱动器
驱动器/接收器数: 2/0
规程: LVDS
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 管件
产品目录页面: 766 (CN2011-ZH PDF)
ADN4663
Rev. 0 | Page 4 of 12
AC CHARACTERISTICS
VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2
Symbol
Min
Typ
Max
Unit
Conditions/Comments3, 4
Differential Propagation Delay High to Low
tPHLD
0.3
0.8
1.5
ns
Differential Propagation Delay Low to High
tPLHD
0.3
1.1
1.5
ns
Differential Pulse Skew |tPHLD tPLHD|5
tSKD1
0
0.3
0.7
ns
Channel-to-Channel Skew6
tSKD2
0
0.4
0.8
ns
Differential Part-to-Part Skew7
tSKD3
0
1.0
ns
Differential Part-to-Part Skew8
tSKD4
0
1.2
ns
Rise Time
tTLH
0.2
0.5
1.0
ns
Fall Time
tTHL
0.2
0.5
1.0
ns
Maximum Operating Frequency9
fMAX
350
MHz
1 CL includes probe and jig capacitance.
2 AC parameters are guaranteed by design and characterization.
3 Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tTLH ≤ 1 ns, and tTHL ≤ 1 ns.
4 All input voltages are for one channel, unless otherwise specified. Other inputs are set to GND.
5 tSKD1 = |tPHLD tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel.
6 tSKD2 is the differential channel-to-channel skew of any event on the same device.
7 tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
8 tSKD4, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
operating temperatures and voltage ranges, and across process distribution. tSKD4 is defined as |maximum minimum| differential propagation delay.
9 fMAX generator input conditions: tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels
switching.
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