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| 型号： | ADP1043AACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 37/72页 |
| 文件大小： | 0K |
| 描述： | IC SECONDARY SIDE CTRLR 32LFCSP |
| 标准包装： | 1 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.55 V |
| 电源电压： | 3.1 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 标准包装 |
| 配用： | ADP1043A-USB-Z-ND - EVAL BOARD DIG POWER SUPPLY |
| 其它名称： | ADP1043AACPZ-RLDKR |
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ADP1043A
Table 14. Register 0x0E—Flag Configuration Register
Bits
7
Name
VDD OV/VCORE OV
R/W
R/W
Description
Setting this bit means that the VDD OV and VCORE OV flags are ignored.
flags ignore
6
VDD OV/VCORE OV
restart
R/W
Setting this bit to 1 means that if the part shuts down, it will download the EEPROM contents
again before restarting. Setting this bit to 0 means that if the part shuts down, it will not
download the EEPROM contents again before restarting.
5
[4:2]
VDD OV/VCORE OV
debounce
Accurate OCP off delay
for CS1 and CS2
R/W
R/W
Setting this bit to 1 means that there is a 500 μs debounce before the part shuts down. Setting
this bit to 0 means that there is a 2 μs debounce before the part shuts down.
When an accurate OCP flag is set, there is a delay before the corresponding action is performed.
This delay is programmed using these bits.
Bit 4
0
0
0
0
1
1
1
1
Bit 3
0
0
1
1
0
0
1
1
Bit 2
0
1
0
1
0
1
0
1
Debounce
1.3 ms
13 ms
130 ms
260 ms
600 ms
1.3 sec
2 sec
2.6 sec
[1:0]
Power supply reenable
time
R/W
These bits specify the time delay before restarting the power supply after a shutdown.
SR1, SR2, and OrFET are reenabled immediately.
Bit 1
Bit 0
Time (sec)
0
0
0.5
0
1
1
1
0
2
1
1
4
Table 15. Register 0x0F—Soft Start Blan k Fault Flags Register
Bits
7
Name
Blank SR
R/W
R/W
Description
Setting this bit means that the SR1 and SR2 PWM outputs are not enabled until the end of the
soft start ramp time.
6
5
4
3
2
Blank OTP
Blank FLAGIN
Blank local OVP
Blank load OVP
Blank CS2 accurate OCP
R/W
R/W
R/W
R/W
R/W
Setting this bit means that the OTP flag is ignored until the end of the soft start ramp time.
Setting this bit means that the FLAGIN flag is ignored until the end of the soft start ramp time.
Setting this bit means that the local OVP flag is ignored until the end of the soft start ramp time.
Setting this bit means that the load OVP flag is ignored until the end of the soft start ramp time.
Setting this bit means that the CS2 accurate OCP flag is ignored until the end of the soft start
ramp time.
1
Blank CS1 accurate OCP
R/W
Setting this bit means that the CS1 accurate OCP flag is ignored until the end of the soft start
ramp time.
0
Blank CS1 fast OCP
R/W
Setting this bit means that the CS1 fast OCP flag is ignored until the end of the soft start ramp time.
Rev. 0 | Page 37 of 72
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