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参数资料
| 型号： | ADP1754ACPZ-1.2-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 1.2V 1.2A 16LFCSP |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 1.2V |
| 输入电压： | 1.6 V ~ 3.6 V |
| 稳压器数量： | 1 |
| 电流 - 输出： | 1.2A（最小值） |
| 电流 - 限制（最小）： | 1.5A |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ EP（4x4） |
| 包装： | 标准包装 |
| 其它名称： | ADP1754ACPZ-1.2-R7DKR |
ADP1754/ADP1755
Data Sheet
1
T
EN
V OUT
As shown in Figure 28, the EN pin has hysteresis built in. This
hysteresis prevents on/off oscillations that can occur due to
noise on the EN pin as it passes through the threshold points.
The EN pin active/inactive thresholds are derived from the VIN
voltage. Therefore, these thresholds vary with changing input
voltage. Figure 29 shows typical EN active/inactive thresholds
when the input voltage varies from 1.6 V to 3.6 V.
1.1
2
500mV/DIV
V OUT = 1.5V
C IN = C OUT = 4.7μF
1.0
CH1 2.0V BW
CH2 500mV BW M40μs
A CH1
920mV
0.9
EN ACTIVE
T 9.8%
Figure 27. V OUT Ramp-Up with Internal Soft Start
0.8
ADJUSTABLE OUTPUT VOLTAGE (ADP1755)
The output voltage of the ADP1755 can be set over a 0.75 V to
3.3 V range. The output voltage is set by connecting a resistive
voltage divider from VOUT to ADJ. The output voltage is calcu-
0.7
0.6
EN INACTIVE
lated using the following equation:
0.5
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
V OUT = 0.5 V × (1 + R1 / R2 )
(2)
INPUT VOLTAGE (V)
where:
R1 is the resistor from VOUT to ADJ.
R2 is the resistor from ADJ to GND.
The maximum bias current into ADJ is 150 nA. Therefore, to
achieve less than 0.5% error due to the bias current, use values
less than 60 k? for R2.
ENABLE FEATURE
The ADP1754/ADP1755 use the EN pin to enable and disable
the VOUT pins under normal operating conditions. As shown
in Figure 28, when a rising voltage on EN crosses the active
threshold, VOUT turns on. When a falling voltage on EN crosses
the inactive threshold, VOUT turns off.
Figure 29. Typical EN Pin Thresholds vs. Input Voltage
POWER-GOOD FEATURE
The ADP1754/ADP1755 provide a power-good pin, PG, to
indicate the status of the output. This open-drain output
requires an external pull-up resistor to V IN. If the part is in
shutdown mode, current-limit mode, thermal shutdown, or
if it falls below 90% of the nominal output voltage, PG imme-
diately transitions low. During soft start, the rising threshold of
the power-good signal is 93.5% of the nominal output voltage.
The open-drain output is held low when the ADP1754/ADP1755
have sufficient input voltage to turn on the internal PG transistor.
An optional soft start delay can be detected. The PG transistor
is terminated via a pull-up resistor to V OUT or V IN .
T
EN
V OUT
Power-good accuracy is 93.5% of the nominal regulator output
voltage when this voltage is rising, with a 90% trip point when
this voltage is falling.
Regulator input voltage brownouts or glitches trigger a power
no-good if V OUT falls below 90%.
A normal power-down triggers a power no-good when V OUT
drops below 90%.
1 2
500mV/DIV
V OUT = 1.5V
C IN = C OUT = 4.7μF
CH1 500mV BW CH2 500mV BW M2.0ms
A CH1
1.05V
T 29.6%
Figure 28. Typical EN Pin Operation
Rev. F | Page 12 of 20
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| ADP1754-BL1-EVZ | 制造商:Analog Devices 功能描述:Evaluation Board Forlow Dropout Linear Regulator 制造商:Analog Devices 功能描述:BLANK ADISIMPOWER EVAL ADP1754 - Boxed Product (Development Kits) |
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