参数资料
型号: ADP1871-1.0-EVALZ
厂商: Analog Devices Inc
文件页数: 38/44页
文件大小: 0K
描述: BOARD EVAL FOR ADP1871-1.0
标准包装: 1
系列: *
ADP1870/ADP1871
(component geometry permitting) that minimizes the area of
flux change as the event switches between D and 1 ? D.
SW
VOUT
LAYER 1: SENSE LINE FOR SW
(DRAIN OF LOWER MOSFET)
Data Sheet
LAYER 1: SENSE LINE FOR PGND
(SOURCE OF LOWER MOSFET)
Figure 91. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS
Amp Differential Sensing (Yellow Sense Line on Layer 2)
Differential sensing should also be applied between the
outermost output capacitor to the feedback resistor divider (see
VIN
PGND
Figure 88 and Figure 89). Connect the positive terminal of the
Figure 90. Primary Current Pathways During the On State of the Upper-Side
MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow)
DIFFERENTIAL SENSING
Because the ADP1870/ADP1871 operate in valley current-
mode control, a differential voltage reading is taken across the
drain and source of the lower-side MOSFET. The drain of the
output capacitor to the top resistor (R T ). Connect the negative
terminal of the output capacitor to the negative terminal of the
bottom resistor, which connects to the analog ground plane as
well. Both of these track lines, as previously mentioned, should
be narrow and away from any other active device or voltage/
current path.
lower-side MOSFET should be connected as close as possible to
the SW pin (Pin 9) of the IC. Likewise, the source should be
connected as close as possible to the PGND pin (Pin 7) of the
IC. When possible, both of these track lines should be narrow
and away from any other active device or voltage/current path.
Rev. B | Page 38 of 44
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