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参数资料
| 型号： | ADP1876-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADP1876 |
| 标准包装： | 1 |
| 系列： | * |
ADP1876
Data Sheet
SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control. V IN = 12 V. The specifications
are valid for T J = ?40°C to +125°C, unless otherwise specified. Typical values are at T A = 25°C.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY
Input Voltage
V IN
2.75
20
V
Undervoltage Lockout Threshold
IN UVLO
V IN rising
2.45
2.6
2.75
V
Undervoltage Lockout Hysteresis
V IN falling
2.4
2.5
0.1
2.6
V
Quiescent Current
Shutdown Current
I IN
I IN_SD
EN1 = EN2 = V IN = 12 V, V FB = V CCO
(no switching)
EN1 = EN2 = GND, V IN = 5.5 V or 20 V
4.5
100
5.9
200
mA
μA
ERROR AMPLIFIER
FB Input Bias Current
I FB
?100
+1
+100
nA
Transconductance
TRK1 Input Bias Current
CURRENT SENSE AMPLIFIER GAIN
g m
I TRK
A CS
Sink or source 1 μA
0 V < V TRK1 < 1.5 V
Gain resistor connected to DLx,
R CSG = 47 kΩ ± 5%
Gain resistor connected to DLx,
385
?100
2.4
5.2
550
+1
3
6
715
+100
3.6
6.9
μS
nA
V/V
V/V
R CSG = 22 kΩ ± 5%
Default setting, R CSG = open
Gain resistor connected to DLx,
10.5
20.5
12
24
13.5
26.5
V/V
V/V
R CSG = 100 kΩ ± 5%
OUTPUT CHARACTERICTISTICS
Feedback Accuracy Voltage
V FB
T J = ?40°C to +85°C, V FB = 0.6 V
T J = ?40°C to +125°C, V FB = 0.6 V
?0.85%
?1.5%
+0.6
+0.6
+0.85%
+1.5%
V
V
Line Regulation of PWM
ΔV FB /ΔV IN
±0.015
%/V
Load Regulation of PWM
ΔV FB /ΔV COMP
V COMP range 0.9 V to 2.2 V
±0.3
%
Oscillator Frequency
f OSC
475
600
690
kHz
LINEAR REGULATOR VCCO
VCCO Output Voltage
VCCO Load Regulation
VCCO Line Regulation
VCCO Short-Circuit Current 1
VIN to VCCO Dropout Voltage 2
V DROPOUT
T A = 25°C, I VCCO = 100 mA
T J = ?40°C to +125°C
I VCCO = 0 mA to 100 mA,
V IN = 5.5 V to 20 V, I VCCO = 20 mA
VCCO < 0.5 V
I VCCO = 100 mA, V IN ≤ 5 V
4.8
4.7
5.0
5.0
35
10
370
0.33
5.18
5.3
400
V
V
mV
mV
mA
V
LOGIC INPUTS
EN1, EN2 Threshold
EN1/EN2 rising
0.57
0.63
0.68
V
EN1, EN2 Hysteresis
0.03
V
EN1, EN2 Input Leakage Current
I EN
V IN = 2.75 V to 20 V
1
200
nA
GATE DRIVERS (DHx, DLx PINS)
DHx Rise Time
DHx Fall Time
DLx Rise Time
DLx Fall Time
DHx to DLx Dead Time
C DH = 3 nF, V BST ? V SW = 5 V
C DH = 3 nF, V BST ? V SW = 5 V
C DL = 3 nF
C DL = 3 nF
External 3 nF capacitor is connected to
16
14
16
14
25
ns
ns
ns
ns
ns
DHx and DLx
Rev. A | Page 4 of 24
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