参数资料
型号: ADP1879-1.0-EVALZ
厂商: Analog Devices Inc
文件页数: 28/40页
文件大小: 0K
描述: BOARD EVAL FOR ADP1879-1.0
标准包装: 1
系列: *
ADP1878/ADP1879
power dissipation across the internal LDO. Equation 3 shows the
power dissipation calculations for the integrated drivers and for
the internal LDO. Table 9 lists the thermal impedance for the
Data Sheet
The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:
ADP1878 / ADP1879 , which are available in a 14-lead LFCSP_WD.
Table 9. Thermal Impedance for 14-Lead LFCSP_WD
T R = θ JA × P DR(LOSS)
where:
(2)
Package
14-Lead LFCSP_WD θ JA
4-Layer Board
Thermal Impedance
30°C/W
θ JA is the thermal resistance of the package from the junction to
the outside surface of the die, where it meets the surrounding air.
P DR(LOSS) is the overall power dissipated by the IC.
Figure 85 specifies the maximum allowable ambient temperature
that can surround the ADP1878 / ADP1879 IC for a specified
high input voltage (V IN ). Figure 85 illustrates the temperature
derating conditions for each available switching frequency for
low, typical, and high output setpoints for the 14-lead LFCSP_WD
package. All temperature derating criteria are based on a
The bulk of the power dissipated is due to the gate capacitance of
the external MOSFETs and current running through the on-board
LDO. The power loss equations for the MOSFET drivers and
internal low dropout regulator (see the MOSFET Driver Loss
section and the Efficiency Consideration section) are:
P DR(LOSS) = [ V DR × ( f SW C upperFET V DR + I BIAS )] +
maximum IC junction temperature of 125°C.
130
[ V REG × ( f SW C lowerFET V REG + I BIAS )]
where:
(3)
C upperFET is the input gate capacitance of the high-side MOSFET.
120
110
100
C lowerFET is the input gate capacitance of the low-side MOSFET.
I BIAS is the dc current (2 mA) flowing into the high- and low-
side drivers.
V DR is the driver bias voltage (the low input voltage (V REG ) minus
the rectifier drop (see Figure 83)).
V REG is the LDO output/bias voltage.
P DISS(LDO) = P DR(LOSS) + ( V IN – V REG ) × ( f SW × C TOTAL ×
300kHz
600kHz
V OUT = 0.8V
V OUT = 1.8V
V REG + I BIAS
(4)
1MHz
V OUT = HIGH SETPOINT
where P DISS(LDO) is the power dissipated through the pass device
90
5.5
7.0
8.5
10.0
11.5
13.0
14.5
16.0
17.5
19.0
in the LDO block across V IN and V REG .
V IN (V)
Figure 85. Ambient Temperature vs. V IN ,
4-Layer Evaluation Board, C IN = 4.3 nF (High-/Low-Side MOSFET)
The maximum junction temperature allowed for the ADP1878 /
ADP1879 IC is 125°C. This means that the sum of the ambient
temperature (T A ) and the rise in package temperature (T R ), which is
caused by the thermal impedance of the package and the internal
power dissipation, should not exceed 125°C, as dictated by the
following expression:
P DR(LOSS) is the MOSFET driver loss.
V IN is the high voltage input.
V REG is the LDO output voltage and bias voltage.
C TOTAL is the C GD + C GS of the external MOSFET.
I BIAS is the dc input bias current.
For example, if the external MOSFET characteristics are θ JA
(14-lead LFCSP_WD) = 30°C/W, f SW = 300 kHz, I BIAS = 2 mA,
C upperFET = 3.3 nF, C lowerFET = 3.3 nF, V DR = 4.62 V, and V REG = 5.0 V,
then the power loss is
T J = T R × T A
where:
T J is the maximum junction temperature.
T R is the rise in package temperature due to the power
dissipated from within.
T A is the ambient temperature.
(1)
P DR(LOSS) = [ V DR × ( f SWCupperFET V DR + I BIAS )] +
[ V REG × ( f SWClowerFET V REG + I BIAS )]
= (4.62 × (300 × 10 3 × 3.3 × 10 ?9 × 4.62 + 0.002)) +
(5.0 × (300 × 10 3 × 3.3 × 10 ?9 × 5.0 + 0.002))
= 57.12 mW
P DISS(LDO) = ( V IN – V REG ) × ( f SW × C TOTAL × V REG + I BIAS ) =
(13 V – 5 V) × (300 × 10 3 × 3.3 × 10 ?9 × 5 + 0.002)
= 55.6 mW
P DISS(TOTAL) = P DISS(LDO) + P DR(LOSS)
= 77.13 mW + 55.6 mW
= 132.73 mW
Rev. B | Page 28 of 40
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