参数资料
型号: ADP2107-1.8-EVALZ
厂商: Analog Devices Inc
文件页数: 27/36页
文件大小: 0K
描述: BOARD EVAL FOR ADP2107-1.8
产品培训模块: Powering 90nm/65nm FPGAs and Processors
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.8V
电流 - 输出: 2A
输入电压: 2.7 ~ 5.5 V
稳压器拓扑结构: 降压
频率 - 开关: 1.2MHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ADP2107
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Data Sheet
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
ADP2105/ADP2106/ADP2107
Good circuit board layout is essential to obtaining the best
performance from the ADP2105/ADP2106/ADP2107. Poor
circuit layout degrades the output ripple, as well as the
electromagnetic interference (EMI) and electromagnetic
compatibility (EMC) performance.
Figure 54 and Figure 55 show the ideal circuit board layout for
the ADP2105/ADP2106/ADP2107 to achieve the highest
performance. Refer to the following guidelines if adjustments to
the suggested layout are needed:
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?
Make the high current path from the PGND pin through L
and C OUT back to the PGND plane as short as possible. To
accomplish this, ensure that the PGND pin is tied to the
PGND plane as close as possible to the input and output
capacitors.
The feedback resistor divider network is to be placed as
close as possible to the FB pin to prevent noise pickup. The
length of trace connecting the top of the feedback resistor
divider to the output is to be as short as possible while
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?
?
?
Use separate analog and power ground planes. Connect
the ground reference of sensitive analog circuitry (such as
compensation and output voltage divider components) to
analog ground; connect the ground reference of power
components (such as input and output capacitors) to power
ground. In addition, connect both the ground planes to the
exposed pad of the ADP2105/ADP2106/ADP2107.
For each PWIN pin, place an input capacitor as close to the
PWIN pin as possible and connect the other end to the closest
power ground plane.
Place the 0.1 μF, 10 Ω low-pass input filter between the IN
pin and the PWIN1 pin, as close to the IN pin as possible.
Ensure that the high current loops are as short and as wide
as possible. Make the high current path from C IN through
L, C OUT , and the PGND plane back to C IN as short as possible.
To accomplish this, ensure that the input and output
?
keeping away from the high current traces and the LX
(switch) node that can lead to noise pickup. An analog
ground plane is to be placed on either side of the FB trace
to reduce noise pickup. For the low fixed voltage options
(1.2 V and 1.5 V), poor routing of the OUT_SENSE trace
can lead to noise pickup, adversely affecting load regulation.
This can be fixed by placing a 1 nF bypass capacitor close to
the FB pin.
The placement and routing of the compensation components
are critical for proper behavior of the ADP2105/ADP2106/
ADP2107. The compensation components are to be placed
as close to the COMP pin as possible. It is advisable to use
0402-sized compensation components for closer placement,
leading to smaller parasitics. Surround the compensation
components with an analog ground plane to prevent noise
pickup. The metal layer under the compensation components
is to be the analog ground plane.
capacitors share a common PGND plane.
Rev. D | Page 27 of 36
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