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| 型号： | ADP2140ACPZ3328R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/32页 |
| 文件大小： | 2731K |
| 描述： | IC REG DL BCK/LINEAR 10LFCSP |
| 标准包装： | 1 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 3MHz |
| 电压/电流 - 输出 1： | 3.3V，600mA |
| 电压/电流 - 输出 2： | 2.8V，300mA |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 是 |
| 电源电压： | 1.65 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘，CSP |
| 供应商设备封装： | 10-LFCSP-WD（3x3） |
| 包装： | 标准包装 |
| 其它名称： | ADP2140ACPZ3328R7DKR |
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ADP2140
Data Sheet
Rev. A | Page 26 of 32
LDO CAPACITOR SELECTION
Output Capacitor
The ADP2140 LDO is designed for operation with small, space-
saving ceramic capacitors, but functions with most commonly
used capacitors as long as care is taken about the effective series
resistance (ESR) value. The ESR of the output capacitor affects
stability of the LDO control loop. A minimum of 0.70 礔 capa-
citance with an ESR of 1 & or less is recommended to ensure
stability of the ADP2140. Transient response to changes in load
current is also affected by output capacitance. Using a larger
value of output capacitance improves the transient response of
the ADP2140 to large changes in load current. Figure 87 shows
the transient response for an output capacitance value of 1 礔.
CH1 100mA
CH2 100mV
M40.0祍
A CH1 68mA
T 10.40%
T
LOAD CURRENT
V
OUT2
Figure 87. Output Transient Response, V
OUT2
= 1.8 V, C
OUT
= 1 礔,
1 mA to 300 mA, Load Current Rise Time = 200 ns
Input Bypass Capacitor
Connecting a 1 礔 capacitor from VIN to GND reduces the cir-
cuit sensitivity to the PCB layout, especially when long input
traces or high source impedance are encountered. If greater than
1 礔 of output capacitance is required, increase the input
capacitor to match it.
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP2140, as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended for best performance.
Y5V and Z5U dielectrics are not recommended for use with any
LDO because of their poor temperature and dc bias characteristics.
Figure 88 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 礔, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ?5% over the 40癈 to +85癈 tempera-
ture range and is not a function of package or voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
VOLTAGE V
MURATA PART NUMBER:
GRM155R61A105KE15
Figure 88. Capacitance vs. Voltage Characteristic
Use Equation 1 to determine the worst-case capacitance accounting
for capacitor variation over temperature, component tolerance, and
voltage.
C
EFF
= C
BIAS
?(1 TEMPCO) ?(1 TOL)
(1)
where:
C
BIAS
is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over 40癈 to +85癈 is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and C
BIAS
is 0.94 糉 at 1.8 V as shown in Figure 88.
Substituting these values in Equation 1 yields
C
EFF
= 0.94 糉 ?(1 0.15) ?(1 0.1) = 0.719 糉
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temper-
ature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP2140, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors are evaluated for each application.
LDO AS A POSTREGULATOR TO REDUCE BUCK
OUTPUT NOISE
The output of the buck regulator may not be suitable for many
noise sensitive applications because of its inherent switching
noise. This is particularly true when the buck is operating in
PSM mode because the switching noise may be in the audio
range. The ADP2140 LDO can greatly reduce the noise at the
output of the buck at high efficiency because of the load dropout
voltage of the LDO and the high PSRR of the LDO. Figure 89
and Figure 90 show the noise reduction that is possible when
the LDO is used as a post regulator.
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