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参数资料
| 型号： | ADP2504ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK BST SYNC ADJ 10LFCSP |
| 产品变化通告： | Reliability Change 27/Apr/2012 |
| 标准包装： | 1 |
| 类型： | 降压（降压），升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 2.8 V ~ 5.5 V |
| 输入电压： | 2.3 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 2.5MHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘，CSP |
| 包装： | 标准包装 |
| 供应商设备封装： | 10-LFCSP-WD（3x3） |
| 产品目录页面： | 791 (CN2011-ZH PDF) |
| 其它名称： | ADP2504ACPZ-R7DKR |
Data Sheet
THEORY OF OPERATION
SW1
4
1.5μH
2
SW2
ADP2503/ADP2504
8
VIN
ADP2503/ADP2504
BIASING
ADP2503/ADP2504
VBAT = 2.3V
TO 5.5V
5
PVIN
PMOS1
PMOS2
VOUT
1
10μF
2.25V
NMOS1
NMOS2
SOFT START
22μF
UVLO
FB
BAND GAP
REFERENCE
THERMAL
PROTECTION
–0.5V
10
EN
6
7
EN
SYNC
PWM CONTROL
OSCILLATOR
CS
PGND
3
AGND
9
Figure 29. ADP2503/ADP2504 Block Diagram
The ADP2503/ADP2504 are synchronous average current-
mode switching buck-boost regulators designed to maintain a
fixed output voltage V OUT from an input supply V IN that can be
greater than, equal to, or less than V OUT . When V IN is signifi-
cantly greater than V OUT , the device is in buck mode: PMOS2 is
always active, NMOS2 is always off, and the PMOS1 and NMOS1
switches constitute a buck converter. When V IN is significantly
lower than V OUT , the device is in boost mode: PMOS1 is always
active, NMOS1 is always off, and the NMOS2 and PMOS2
switches constitute a boost converter. When V IN is in the range
[V OUT ± 10%], the ADP2503/ADP2504 automatically enter the
buck-boost mode. In buck-boost mode, the two operations,
buck (PMOS1 and NMOS1 switching in antiphase) and boost
(NMOS2 and PMOS2 switching in antiphase), take place at each
period of the clock. This is aimed at maintaining the regulation
and keeping a minimal current ripple in the inductor to guaran-
tee good transient performances.
POWER SAVE MODE
When the SYNC pin is low, the ADP2503/ADP2504 can operate
in power save mode (PSM). In this mode, when the load current
becomes less than 75 mA nominally at V IN = 3.6 V, the control-
ler pulls up V OUT and then halts the switching regime until V OUT
goes back to a restart value. Then V OUT is pulled up again for a
new cycle. This minimizes the switching losses at light load. When
the load rises above 150 mA, the ADP2503/ADP2504 revert to
fixed PWM mode. This results in about 75 mA of hysteresis
between PSM and fixed PWM, preventing oscillations between
these two modes.
SOFT START
When the ADP2503/ADP2504 are started, V OUT is ramped from
0 V to its final programmed value in 200 μs (typical). This limits
the inrush current to less than 600 mA for a nominal output
capacitor of 20 μF. Because the V OUT start-up slope is constant,
the inrush current becomes larger if the output capacitor is
made larger.
SYNC FUNCTION
When the SYNC pin is high, PSM is deactivated. The ADP2503/
ADP2504 always operate in PWM using the internal oscillator.
When the SYNC pin is switching in the 2.1 MHz to 2.9 MHz
range, the regulator switching frequency slides to the fre-
quency applied on SYNC and then locks on it. When the
SYNC pin stops switching, the regulator switching frequency
slides back to the internal oscillator frequency.
ENABLE
The device starts operation with soft start when the EN pin
is brought high. Pulling the EN pin low forces the device into
shutdown, with a typical shutdown current of 0.2 μA.
In this mode, the PMOS power switches are turned off, the
NMOS power switches are turned on, and the control circuitry
is not enabled. For proper operation, the EN pin must be
terminated and must not be left floating.
Rev. C | Page 11 of 16
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