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参数资料
| 型号： | ADP3170JRU-REEL |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, PDSO20 |
| 封装： | TSSOP-20 |
| 文件页数： | 6/16页 |
| 文件大小： | 177K |
| 代理商： | ADP3170JRU-REEL |
REV. 0
ADP3170
–14–
LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The following guidelines are recommended for optimal perfor-
mance of a switching regulator in a PC system:
General Recommendations
1.
For best results, a four-layer PCB is recommended. This
should allow the needed versatility for control circuitry
interconnections with optimal placement, a signal ground
plane, power planes for both power ground and the input
power (e.g., 5 V), and wide interconnection traces in the
rest of the power delivery current paths.
2.
Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several
parallel current paths so that the resistance and induc-
tance introduced by these current paths is minimized and
the via current rating is not exceeded.
3.
If critical signal lines (including the voltage and current
sense lines of the ADP3170) must cross through power cir-
cuitry, it is best if a ground plane can be interposed between
those signal lines and the traces of the power circuitry. This
serves as a shield to minimize noise injection into the signals
at the expense of making signal ground a bit noisier.
4.
The GND pin of the ADP3170 should connect first to a
ceramic bypass capacitor (on the VCC pin) and then into the
analog ground plane. The analog ground plane should be
located below the ADP3170 and the surrounding small-
signal components, such as, the timing capacitor and
compensation network. The analog ground plane should
connect to power ground plane at a single point; the best
location being the negative terminal of the last output
capacitor.
5.
The output capacitors should also be connected as closely as
possible to the load (or connector) that receives the power
(e.g., a microprocessor core). If the load is distributed,
the capacitors too should be distributed, and generally in
proportion to where the load tends to be more dynamic. It is
advised to keep the planar interconnection path short
(i.e., have input and output capacitors close together).
6.
Absolutely avoid crossing any signal lines over the switching
power path loop, described below.
Power Circuitry
7. The switching power path should be routed on the PCB to
encompass the smallest possible area in order to minimize
radiated switching noise energy (i.e., EMI). Failure to take
proper precaution often results in EMI problems for the
entire PC system, as well as, noise-related operational
problems in the power converter control circuitry. The
switching power path is the loop formed by the current
path through the input capacitors, the two FETs and the
power Schottky diode, if used, including all intercon-
necting PCB traces and planes. The use of short and wide
interconnection traces is especially critical in this path for
two reasons: it minimizes the inductance in the switching
loop, which can cause high-energy ringing; and it accom-
modates the high current demand with minimal voltage loss.
8.
A power Schottky diode (1 ~ 2 A dc rating) placed from
the lower MOSFET’s source (anode) to drain (cathode)
will help to minimize switching power dissipation in the
upper MOSFET. In the absence of an effective Schottky
diode, this dissipation occurs through the following sequence
of switching events. The lower MOSFET turns off in
advance of the upper MOSFET turning on (necessary to
prevent cross-conduction). The circulating current in the
power converter, no longer finding a path for current
through the channel of the lower MOSFET, draws current
through the inherent body-drain diode of the MOSFET.
The upper MOSFET turns on, and the reverse recovery
characteristic of the lower MOSFET’s body-drain diode
prevents the drain voltage from being pulled high quickly.
The upper MOSFET then conducts very large current
while it momentarily has a high voltage forced across it,
which translates into added power dissipation in the upper
MOSFET. The Schottky diode minimizes this problem
by carrying a majority of the circulating current when the
lower MOSFET is turned off, and by virtue of its essen-
tially nonexistent reverse recovery time.
9.
Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately sur-
rounding it, is recommended. Two important reasons for
this are: improved current rating through the vias (if it is
a current path); and improved thermal performance—
especially if the vias extended to the opposite side of the PCB
where a plane can more readily transfer the heat to the air.
10. The output power path, though not as critical as the switch-
ing power path, should also be routed to encompass a small
area. The output power path is formed by the current path
through the inductor, the current sensing resistor, the out-
put capacitors, and back to the input capacitors.
11. For best EMI containment, the ground plane should extend
fully under all the power components. These are: the input
capacitors, the power MOSFETs and Schottky diode, the
inductor, the current sense resistor, any snubbing elements
that might be added to dampen ringing and the output
capacitors.
Signal Circuitry
12. The output voltage is sensed and regulated between the
GND pin (which connects to the signal ground plane) and
the CS– pin. The output current is sensed (as a voltage)
and regulated between the CS– pin and the CS+ pin. In
order to avoid differential mode noise pickup in those
sensed signals, their loop areas should be small. Thus the
CS– trace should be routed atop the signal ground plane,
and the CS+ and CS– traces should be routed as a closely
coupled pair (CS+ should be over the signal ground plane
as well).
13. The CS+ and CS– traces should be Kelvin connected to
the current sense resistor so that the additional voltage drop
due to current flow on the PCB at the current sense resistor
connections does not affect the sensed voltage. It is desirable
to have the ADP3170 close to the output capacitor bank
and not in the output power path, so that any voltage drop
between the output capacitors and the GND pin is mini-
mized, and voltage regulation is not compromised.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP3170JRU-REEL7 | 制造商:Analog Devices 功能描述: |
| ADP3170JRUZ-R7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADP3170JRUZ-REEL7 | 功能描述:IC CTRLR VRM 8.5 W/REG 20TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ADP3171 | 制造商:AD 制造商全称:Analog Devices 功能描述:Synchronous Buck Controller with Dual Linear Regulator Controllers |
| ADP3171JR | 制造商:Rochester Electronics LLC 功能描述:1.2V VTT BUCK CNTRLR W/2 LDOS & PWR GOOD - Bulk |
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