参数资料
型号: ADP3211MNR2G
厂商: ON Semiconductor
文件页数: 29/32页
文件大小: 0K
描述: IC CTLR BUCK 7BIT 2PHASE 32QFN
标准包装: 5,000
应用: 控制器,用于下一代 Intel 处理器的电源
输入电压: 3.3 V ~ 22 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 带卷 (TR)
ADP3211, ADP3211A
7. Measure the output ripple with no load and with a
full load with scope, making sure both are within
the specifications.
Set the AC Load Line
1. Remove the dc load from the circuit and connect
a dynamic load.
2. Connect the scope to the output voltage and set it
to dc coupling mode with a time scale of
100 m s/div.
3. Set the dynamic load for a transient step of about
40 A at 1 kHz with 50% duty cycle.
4. Measure the output waveform (note that use of a
dc offset on the scope may be necessary to see the
waveform). Try to use a vertical scale of
100 mV/div or finer.
5. The resulting waveform will be similar to that
shown in Figure 37. Use the horizontal cursors to
9. Ensure that the load step slew rate and the
powerup slew rate are set to ~150 A/ m s to
250 A/ m s (for example, a load step of 10 A should
take 50 ns to 100 ns) with no overshoot. Some
dynamic loads have an excessive overshoot at
powerup if a minimum current is incorrectly set
(this is an issue if a VTT tool is in use).
Set the Initial Transient
1. With the dynamic load set at its maximum step
size, expand the scope time scale to 2 m s/div to
5 m s/div. This results in a waveform that may
have two overshoots and one minor undershoot
before achieving the final desired value after
V DROOP (see Figure 38).
measure V ACDRP and V DCDRP , as shown in
Figure 37. Do not measure the undershoot or
overshoot that occurs immediately after the step.
V TRAN1
V TRAN2
V DROOP
V ACDRP
V DCDRP
Figure 38. Transient Setting Waveform, Load Step
2. If both overshoots are larger than desired, try the
following adjustments in the order shown.
a. Increase the resistance of the ramp resistor
(R RAMP ) by 25%.
V ACDRP
V DCDRP
Figure 37. AC Load Line Waveform
6. If the difference between V ACDRP and V DCDRP is
more than a couple of millivolts, use Equation 47
to adjust C CS . It may be necessary to try several
parallel values to obtain an adequate one because
there are limited standard capacitor values
available (it is a good idea to have locations for
two capacitors in the layout for this reason).
C CS(NEW) + C CS(OLD) (eq. 47)
7. Repeat Steps 5 and 6 until no adjustment of C CS
is needed. Once this is achieved, do not change
C CS for the rest of the procedure.
8. Set the dynamic load step to its maximum step
size (but do not use a step size that is larger than
needed) and verify that the output waveform is
square, meaning V ACDRP and V DCDRP are equal.
b. For V TRAN1 , increase C B or increase the
switching frequency.
c. For V TRAN2 , increase R A by 25% and decrease
C A by 25%.
If these adjustments do not change the response, it
is because the system is limited by the output
decoupling. Check the output response and the
switching nodes each time a change is made to
ensure that the output decoupling is stable.
3. For load release (see Figure 39), if V TRANREL is
larger than the value specified by IMVP ? 6.5, a
greater percentage of output capacitance is
needed. Either increase the capacitance directly
or decrease the inductor values. (If inductors are
changed, however, it will be necessary to
redesign the circuit using the information from
the spreadsheet and to repeat all tuning guide
procedures).
http://onsemi.com
29
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