参数资料
型号: ADP3303ARZ-5
厂商: Analog Devices Inc
文件页数: 10/16页
文件大小: 0K
描述: IC REG LDO 5V .2A 8-SOIC
设计资源: Precision Weigh Scale Design Using AD7190 with Internal PGA (CN0102)
Precision Weigh Scale Design Using AD7191 with Internal PGA (CN0118)
Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119)
Precision Weigh Scale Design Using AD7195 with Internal PGA and AC Excitation (CN0155)
标准包装: 98
系列: anyCAP®
稳压器拓扑结构: 正,固定式
输出电压: 5V
输入电压: 最高 12V
电压 - 压降(标准): 0.18V @ 200mA
稳压器数量: 1
电流 - 输出: 200mA
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
产品目录页面: 794 (CN2011-ZH PDF)

ADP3303
APPLICATION INFORMATION
CAPACITOR SELECTION
Output Capacitors
As with any micropower device, output transient response is a
function of the output capacitance. The ADP3303 is stable with
a wide range of capacitor values, types and ESR. A capacitor as
low as 0.47 μF is all that is needed for stability; larger capacitors
can be used if high output current surges are anticipated. The
ADP3303 is stable with extremely low ESR capacitors (ESR ≈ 0),
such as multilayer ceramic capacitors (MLCC) or OSCON.
Input Bypass Capacitor
An input bypass capacitor is not required. For applications in
which the input source is high impedance or far from the input
pins, use a bypass capacitor. Connecting a 0.47 μF capacitor
from the input pins to ground reduces the sensitivity of the
circuit to PCB layout. If a larger value output capacitor is used,
then a larger value input capacitor is also recommended.
NOISE REDUCTION
A noise reduction capacitor (C NR ) can be used to further reduce
the noise by 6 dB to 10 dB (see Figure 23). Low leakage capacitors
in the 10 nF to 100 nF range provide the best performance.
Since the noise reduction pin (NR) is internally connected to a
high impedance node, any connection to this node must be
carefully done to avoid noise pickup from external sources. The
pad connected to this pin must be as small as possible. Long
PCB traces are not recommended.
Data Sheet
CALCULATING JUNCTION TEMPERATURE
Device power dissipation is calculated as follows:
P D = (V IN – V OUT ) I LOAD + (V IN ) I GND
where:
I LOAD and I GND are load current and ground current.
V IN and V OUT are input and output voltages, respectively.
Assuming I LOAD = 200 mA, I GND = 2 mA, V IN = 7 V and V OUT =
5.0 V, device power dissipation is:
P D = (7 V – 5 V) 200 mA + (7 V) 2 mA = 414 mW
The proprietary package used in the ADP3303 has a thermal
resistance of 96°C/W, significantly lower than a standard 8-lead
SOIC_N package at 170°C/W.
Junction temperature above ambient temperature is
approximately equal to:
0.414 W × 96°C/W = 39.7°C
To limit the maximum junction temperature to 125°C,
maximum ambient temperature must be lower than:
T AMAX = 125°C – 40°C = 85°C
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATION
All surface mount packages rely on the traces of the PCB to
conduct heat away from the package.
In standard packages, the dominant component of the heat
V IN
C1 +
1μF
7
8
NR 3
ADP3303-5.0
1
IN OUT
2
ERR 6
SD GND
C NR
10nF
R1
330 kΩ
E OUT
+
V OUT = 5V
C2
10μF
resistance path is the plastic between the die attach pad and the
individual leads. In typical thermally enhanced packages, one or
more of the leads are fused to the die attach pad, significantly
decreasing this component. To make the improvement meaningful,
however, a significant copper area on the PCB must be attached
to these fused pins.
5
ON
OFF
4
The patented thermal coastline lead frame design of the ADP3303
(see Figure 24) uniformly minimizes the value of the dominant
portion of the thermal resistance. It ensures that heat is conducted
SD
Figure 23. Noise Reduction Circuit
THERMAL OVERLOAD PROTECTION
The ADP3303 is protected against damage due to excessive power
dissipation by its thermal overload protection circuit, which
limits the die temperature to a maximum of 165°C. Under
extreme conditions (that is, high ambient temperature and
power dissipation), where die temperature starts to rise above
165°C, the output current is reduced until the die temperature
away by all pins of the package. This yields a very low, 96°C/W,
thermal resistance for an SOIC_N package, without any special
board layout requirements, relying on the normal traces connected
to the leads. The thermal resistance can be decreased approximately
an additional 10% by attaching a few square cm of copper area
to the IN pin of the ADP3303 .
Do not use solder mask or silkscreen on the PCB traces
adjacent to the pins of the ADP3303 since it increases the
junction to ambient thermal resistance of the package.
drops to a safe level. The output current is restored when the
die temperature is reduced.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation must be externally limited
so that junction temperatures does not exceed 125°C.
Rev. C | Page 10 of 16
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