参数资料
型号: ADP3418KRZ1
厂商: Analog Devices, Inc.
英文描述: Dual Bootstrapped 12 V MOSFET Driver with Output Disable
中文描述: 12伏双自举MOSFET驱动器与输出禁用
文件页数: 10/16页
文件大小: 323K
代理商: ADP3418KRZ1
ADP3418
APPLICATION INFORMATION
SUPPLY CAPACITOR SELECTION
For the supply input (VCC) of the ADP3418, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 4.7 μF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size. Keep the
ceramic capacitor as close as possible to the ADP3418.
Rev. B | Page 10 of 16
BOOTSTRAP CIRCUIT
The bootstrap circuit uses a charge storage capacitor (C
BST
) and
a diode, as shown in Figure 1. These components can be
selected after the high-side MOSFET has been chosen. The
bootstrap capacitor must have a voltage rating that is able to
handle twice the maximum supply voltage. A minimum 50 V
rating is recommended. The capacitor values are determined
using the following equations:
Q
C
C
×
=
+
10
GATE
V
V
GATE
BST2
BST1
(1)
D
GATE
BST2
BST1
BST1
+
V
VCC
C
C
C
=
(2)
where
Q
GATE
is the total gate charge of the high-side MOSFET at
V
GATE
, V
GATE
is the desired gate drive voltage (usually in the
range of 5-10 V, 7 V being typical), and V
D
is the voltage drop
across D1. Rearranging Equations 1 and 2 to solve for C
BST1
yields
D
GATE
BST1
V
VCC
Q
C
×
=
10
C
BST2
can then be found by rearranging Equation 1:
1
10
BST
GATE
V
GATE
BST2
C
Q
C
×
=
For example, an NTD60N02 has a total gate charge of about
12 nC at V
GATE
= 7 V. Using VCC = 12 V and V
D
= 1 V, we find
C
BST1
= 12 nF and C
BST2
= 6.8 nF. Good quality ceramic
capacitors should be used.
R
BST
is used for slew-rate limiting to minimize the ringing at the
switch node. It also provides peak current limiting through D1.
An R
BST
value of 1.5 to 2.2 is a good choice. The resistor
needs to be able to handle at least 250 mW due to the peak
currents that flow through it.
A small-signal diode can be used for the bootstrap diode due to
the ample gate drive voltage supplied by V
CC
. The bootstrap
diode must have a minimum 15 V rating to withstand the
maximum supply voltage. The average forward current can be
estimated by
MAX
GATE
AVG
F
f
Q
I
)
(
×
=
(3)
where
f
MAX
is the maximum switching frequency of the
controller. The peak surge current rating should be calculated
using:
V
VCC
I
=
)
(
BST
D
PEAK
F
R
(4)
MOSFET SELECTION
When interfacing the ADP3418 to external MOSFETs, there are
a few considerations that the designer should be aware of. These
will help to make a more robust design that will minimize
stresses on both the driver and MOSFETs. These stresses
include exceeding the short-time duration voltage ratings on
the driver pins as well as the external MOSFET.
It is also highly recommended to use the Boot-Snap circuit to
improve the interaction of the driver with the characteristics of
the MOSFETs. If a simple bootstrap arrangement is used, make
sure to then include a proper snubber network on the SW node.
High-Side (Control) MOSFETs
The high-side MOSFET is usually selected to be high speed to
minimize switching losses (see any ADI Flex-mode controller
datasheet for more details on MOSFET losses). This usually
implies a low gate resistance and low input capacitance/charge
device. Yet, there is also a significant source lead inductance that
can exist (this depends mainly on the MOSFET package; it is
best to contact the MOSFET vendor for this information).
The ADP3418 DRVH output impedance and the input
resistance of the MOSFETs determine the rate of charge
delivery to the gate’s internal capacitance, which determines the
speed at which the MOSFETs turn on and off. However, due to
potentially large currents flowing in the MOSFETs at the on and
off times (this current is usually larger at turn off due to
ramping up of the output current in the output inductor), the
source lead inductance will generate a significant voltage across
it when the high-side MOSFETs switch off. This will create a
significant drain-source voltage spike across the internal die of
the MOSFETs and can lead to catastrophic avalanche. The
mechanisms involved in this avalanche condition can be
referenced in literature from the MOSFET suppliers.
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