参数资料
| 型号： | ADP4000JCPZ-RL7 |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/37页 |
| 文件大小： | 0K |
| 描述： | IC PWR CTRL PMBUS 48-LFCSP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi Product Discontinuation 30/Sept/2011 |
| 标准包装： | 750 |
| 应用： | 转换器，Intel VR11，VR11.1 |
| 输入电压： | 4.7 V ~ 5.75 V |
| 输出数： | 6 |
| 输出电压： | 0.38 V ~ 1.8 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 带卷 (TR) |
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ADP4000
Description
The ADP4000 is a 6 ? Phase VR11.1 regulator with an I 2 C
Interface Typical application circuits is shown in Figure 2.
Table 1. Delay Codes
Code
000
Delay (msec)
0.5
Startup Sequence
The ADP4000 follows the VR11 startup sequence shown
in Figure 7. After both the EN and UVLO conditions are
met, a programmable internal timer goes through one delay
cycle TD1. This delay cycle is programmed using Delay
Command, default delay = 2 ms, see Table 1 for
programmable values). The first six clock cycles of TD2 are
blanked from the PWM outputs and used for phase detection
as explained in the following section. Then the
programmable internal soft ? start ramp is enabled (TD2) and
the output comes up to the boot voltage of 1.1 V. The boot
hold time is also set by Delay Command. This second delay
cycle is called TD3. During TD3 the processor VID pins
settle to the required VID code. When TD3 is over, the
ADP4000 reads the VID inputs and soft ? starts either up or
down to the final VID voltage (TD4). After TD4 has been
completed and the PWRGD masking time (equal to VID on
the fly masking) is finished, a third cycle of the internal timer
sets the PWRGD blanking (TD5).
The internal delay and soft ? start times are programmable
using the serial interface and the Delay Command and the
Soft ? Start Commands.
001 1
010 1.5
011 2 = default
100 2.5
101 3
110 3.5
111 4
The delay timer is programmed using Bits <2:0> of the
Ton Delay command (0xD4). The delay can be programmed
between 0.5 msec and 4 msec. Table 1 provides the
programmable delay times.
Soft ? Start
The soft ? start slope for the output voltage is set by an
internal timer. The default value is 0.5 V/msec, which can be
programmed through the I 2 C interface. After TD1 and the
phase detection cycle have been completed, the SS time
(TD2 in Figure 7) starts. The SS circuit uses the internal VID
DAC to increase the output voltage in 6.25 mV steps up to
the 1.1 V boot voltage.
Once the SS circuit has reached the boot voltage, the boot
voltage delay time (TD3) is started. The end of the boot
voltage delay time signals the beginning of the second
5.0 V
SUPPLY
UVLO
THRESHOLD
soft ? start time (TD4). The SS voltage changes from the boot
voltage to the programmed VID DAC voltage (either higher
or lower) using 6.25 mV steps.
VTT I/O
(ADP4000 EN)
VCC_CORE
0.85 V
TD1
TD3
V BOOT
(1.1 V)
V VID
The soft ? start slew rate is programmed using Bits <2:0>
of the Ton_Rise (0xD5) command code. Table 2 provides
the soft ? start values.
TD4
TD2
Table 2. Slew Rate Codes
VR READY
(ADP4000 PWRGD)
Code
Slew Rate (V/msec)
CPU
VID INPUTS
VID INVALID
50 m s
TD5
VID VALID
000
001
010
0.1
0.3
0.5 = default
011
0.7
Figure 7. System Startup Sequence for VR11
Internal Delay Timer
An internal timer sets the delay times for the startup
sequence, TD1, TD3 and TD5. The default time is 2msec,
which can be changed using the I 2 C interface. This timer is
used for multiple delay timings (TD1, TD3 and TD5) during
the startup sequence. Also, it is used for timing the current
limit latchoff as explained in the Current Limit section. The
current limit timer is set to 4 times the delay timer.
http://onsemi.com
11
100
101
110
111
0.9
1.1
1.3
1.5
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