参数资料
| 型号： | ADP4100JCPZ-RL7 |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/22页 |
| 文件大小： | 0K |
| 描述： | IC POWER CTLR VR11.1 48-LFCSP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi Product Discontinuation 30/Sept/2011 |
| 标准包装： | 750 |
| 应用： | 转换器，Intel VR11，VR11.1 |
| 输入电压： | 4.7 V ~ 5.75 V |
| 输出数： | 6 |
| 输出电压： | 0.38 V ~ 1.6 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 带卷 (TR) |
ADP4100
Theory of Operation
The ADP4100 is a 6 ? Phase VR11.1 regulator. A typical
application circuits is shown in Figure 2.
Startup Sequence
The ADP4100 follows the VR11 startup sequence shown
in Figure 7. After both the EN and UVLO conditions are
met, an internal timer goes through one delay cycle
TD1 (= 2ms). The first six clock cycles of TD2 are blanked
from the PWM outputs and used for phase detection as
explained in the following section. Then the internal
soft ? start ramp is enabled (TD2) and the output comes up to
the boot voltage of 1.1V. The voltage is held at 1.1V for the
2 ms, also known as the Boot Hold time or TD3. During TD3
the processor VID pins settle to the required VID code.
When TD3 is over, the ADP4100 reads the VID inputs and
soft ? starts either up or down to the final VID voltage (TD4).
After TD4 has been completed and the PWRGD masking
time (equal to VID on the fly masking) is finished, a third
cycle of the internal timer sets the PWRGD blanking (TD5).
Figure 8 typical startup waveforms:
Channel 1: CSREF
Channel 2: PWM1
Channel 3 : Enable
Phase Detection
During startup, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP4100
operates as a 6 ? Phase PWM controller.
To operate as a 5 ? Phase Controller connect PWM6 to V CC .
To operate as a 4 ? Phase Controller connect PWM5 and
PWM6 to V CC .
To operate as a 3 ? Phase Controller connect PWM4, PWM5
and PWM6 to V CC .
To operate as a 2 ? Phase Controller connect PWM3, PWM4,
PWM5 and PWM6 to V CC .
To operate as a single phase controller connect PMW2,
PWM3, PWM4, PWM5 and PWM6 to V CC .
Prior to soft ? start, while EN is high the PWM6, PWM5,
5V
SUPPLY
UVLO
THRESHOLD
PWM4 PWM3 and PWM2 pins sink approximately 100 m A
each. An internal comparator checks each pin’s voltage vs.
VTT I/O
(ADP4100 EN)
VCC_CORE
VR READY
(ADP4100 PWRGD)
CPU
VID INPUTS
0.85V
TD1
VID INVALID
TD2
TD3
V BOOT
(1.1V)
50 m s
V VID
TD4
TD5
VID VALID
a threshold of 3.0 V. If the pin is tied to V CC , it is above the
threshold. Otherwise, an internal current sink pulls the pin
to GND, which is below the threshold. PWM1 is low during
the phase detection interval that occurs during the first six
clock cycles of TD2. After this time, if the remaining PWM
outputs are not pulled to V CC , the 100 m A current sink is
removed, and they function as normal PWM outputs. If they
are pulled to V CC , the 100 m A current source is removed, and
the outputs are put into a high impedance state.
The PWM outputs are logic ? level devices intended for
driving fast response external gate drivers such as the
Figure 7. System Startup Sequence for VR11
Figure 8 shows typical startup waveforms for the
ADP4100.
ADP3121. Because each phase is monitored independently,
operation approaching 100% duty cycle is possible. In
addition, more than one output can be on at the same time to
allow overlapping phases.
Master Clock Frequency
The clock frequency of the ADP4100 is set with an
external resistor connected from the RT pin to ground. The
frequency follows the graph in Figure 3. To determine the
frequency per phase, the clock is divided by the number of
phases in use. If all phases are in use, divide by 6. If 4 phases
are in use then divide by 4.
R T +
n
1
f sw
C r
* R TO
(eq. 1)
Where: CT = 2.2 pF and RTO = 21 K
Output Voltage Differential Sensing
The ADP4100 combines differential sensing with a high
accuracy VID DAC and reference, and a low offset error
Figure 8. Shows Typical Startup Waveforms for
the ADP4100
amplifier. This maintains a worst ? case specification of
± 7 mV differential sensing error over its full operating
output voltage and temperature range. The output voltage is
sensed between the FB pin and FBRTN pin. FB is connected
http://onsemi.com
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