参数资料
| 型号： | ADP5020ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/28页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO DUAL BUCK 20LFCSP |
| 设计资源： | Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135) |
| 标准包装： | 1 |
| 应用： | 手持/移动设备 |
| 电流 - 电源： | 10mA |
| 电源电压： | 2.4 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 20-LFCSP-VQ |
| 包装： | 标准包装 |
| 产品目录页面： | 795 (CN2011-ZH PDF) |
| 其它名称： | ADP5020ACPZ-R7DKR |
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ADP5020
The application processor, together with the regulator power
After a regulator is enabled and no failure condition is detected
(power good = 1 in Bits[3:1] of the REG_CONTROL_STATUS
register, Address 0x03), the level of the XSHTDN pin is con-
trolled by Bit 0 (FORCE_XS) in the REG_CONTROL_STATUS
register. Therefore, the application processor can write to this
register to gain control over the XSHTDN pin. However, if the
EN signal is high, the level on the XSHTDN pin depends on the
power good condition of the regulator.
Table 18. Truth Table
POWER-UP/POWER-DOWN STATE FLOW
When the device is enabled, the UVLO circuit constantly monitors
the supply voltage. If the supply voltage falls below the V UVLOF
threshold, typically 2.0 V, the regulators are immediately turned
off. All the internal analog circuits are then disabled to save power,
except the power-on reset (POR) circuit, which detects if the supply
voltage is dropping. If the supply voltage is higher than the POR
threshold, the POR circuit keeps the logic circuits operating
properly and retains the internal values of the registers. This
POR threshold is set to approximately 1.4 V.
If the supply voltage goes below the V UVLOR threshold, but not
EN
Power
XSHTDN
below the POR threshold, the registers are preserved. If the supply
Pin
0
0
0
0
1
1
I 2 C Regulator Enable
0
1
1
1
Good
0
X 1
0
1
1
0
FORCE_XS
X 1
0
1
1
X 1
X 1
Pin
0
0
0
1
1
0
voltage returns to the normal operating level (above V UVLOR ),
a new activation does not require initialization of the registers.
However, if the supply voltage goes below the POR level, the
device is held in reset state. When the input voltage resumes the
proper operating level, the host controller must reload the registers.
The additional current required to keep the POR monitoring
circuits alive during UVLO is estimated to be approximately 1 μA.
1
X = don’t care.
NO POWER
VDDx > V POR
LEVEL
VDDx < V POR
INTERNAL
RESET
VDD x < V POR
EN = LOW
EN = LOW AND 1 2 C OFF
COMMAND
OR VDDx < V UVLOF
STAND BY
EN = HIGH
NORMAL
OPERATION
I 2 C
COMMANDS
DEVICE ENABLED
(EN_ALL OR EN = HIGH)
EN = LOW OR I 2 C OFF
COMMAND
OR VDDx < V UVLOF
TSD
STARTUP
SEQUENCER
SEQUENCE
END, AND ALL REGULATIONS ARE
POWER GOOD
Figure 27. State Flow
Rev. 0 | Page 20 of 2 8
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