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| 型号： | ADS1217IPFBT |
| 英文描述： | 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 8通道，24位模拟数字转换器 |
| 文件页数： | 13/28页 |
| 文件大小： | 458K |
| 代理商： | ADS1217IPFBT |
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ADS1217
SBAS260B
13
www.ti.com
VOLTAGE REFERENCE INPUT
The ADS1217 uses a differential voltage reference input.
The input signal is measured against the differential voltage
V
REF
≡
(V
REF+
)
–
(V
REF
–
). For AV
DD
= 5V, V
REF
is typically
2.5V. For AV
DD
= 3V, V
REF
is typically 1.25V. Due to the
sampling nature of the modulator, the reference input current
increases with higher modulator clock frequency (f
MOD
) and
higher PGA settings.
ON-CHIP VOLTAGE REFERENCE
A selectable voltage reference (1.25V or 2.5V) is available for
supplying the voltage reference input. To use, connect V
REF
–
to AGND and V
REF+
to V
REFOUT
. The enabling and voltage
selection are controlled through bits REF EN and REF HI in
the setup register. The 2.5V reference requires AV
DD
= 5V.
When using the on-chip voltage reference, the V
REFOUT
pin
should be bypassed with a 0.1
μ
F capacitor to AGND.
V
RCAP
PIN
This pin provides a bypass cap for noise filtering on internal
V
REF
circuitry only. As this is a sensitive pin, place the
capacitor as close as possible and avoid any resistive load-
ing. The recommended capacitor is a 0.001
μ
F ceramic cap.
If an external V
REF
is used, this pin can be left unconnected.
CLOCK GENERATOR
The clock source for the ADS1217 can be provided from a
crystal, oscillator, or external clock. When the clock source is
a crystal, external capacitors must be provided to ensure start-
up and a stable clock frequency; see Figure 2 and Table I.
FIGURE 3. Filter Step Responses.
SETTLING TIME
(Conversion Cycles)
FILTER
Sinc
3
Sinc
2
Fast
3
2
1
CONVERSION CYCLE
1
2
3
4+
Fast
Sinc
2
Sinc
3
Sinc
3
AUTO MODE FILTER SELECTION
FILTER SETTLING TIME
Adjustable Digital Filter
Data Out
Modulator
Output
Fast Settling
Sinc
2
Sinc
3
complete both an offset and gain calibration. Self-gain cali-
bration is optimized for PGA gains less than 8. When using
higher gains, system gain calibration is recommended.
For system calibration, the appropriate signal must be
applied to the inputs. The system offset command requires a
“
zero
”
differential input signal. It then computes an offset that
will nullify offset in the system. The system gain command
requires a positive
“
full-scale
”
differential input signal. It then
computes a value to nullify gain errors in the system. Each of
these calibrations will take seven t
DATA
periods to complete.
Calibration must be performed after power on, a change in
decimation ratio, or a change of the PGA. For operation with
a reference voltage greater than (AV
DD
–
1.5V), the buffer
must also be turned off during calibration.
At the completion of calibration, the
DRDY
signal goes LOW,
which indicates the calibration is finished and valid data is
available. See Application Report Calibration Routine and
Register Value Generation for the ADS121x Series(SBAA099)
for more information.
DIGITAL FILTER
The Digital Filter can use either the fast settling, sinc
2
, or
sinc
3
filter, as shown in Figure 3. In addition, the Auto mode
changes the sinc filter after the input channel or PGA is
changed. When switching to a new channel, it will use the
fast settling filter; It will then use the sinc
2
followed by the
sinc
3
filter. This combines the low-noise advantage of the
sinc
3
filter with the quick response of the fast settling time
filter. See Figure 4 for the frequency response of each filter.
When using the fast setting filter, select a decimation value
set by the DEC0 and M/DEC1 registers that is evenly
divisible by four for the best gain accuracy. For example,
choose 260 rather than 261.
FIGURE 2. Crystal Connection.
CLOCK
SOURCE
PART
NUMBER
FREQUENCY
C
1
C
2
Crystal
Crystal
Crystal
Crystal
2.4576
4.9152
4.9152
4.9152
0-20pF
0-20pF
0-20pF
0-20pF
0-20pF
0-20pF
0-20pF
0-20pF
ECS, ECSD 2.45 - 32
ECS, ECSL 4.91
ECS, ECSD 4.91
CTS, MP 042 4M9182
TABLE I. Typical Clock Sources.
C
1
Crystal
X
IN
X
OUT
C
2
CALIBRATION
The offset and gain errors in the ADS1217, or the complete
system, can be reduced with calibration. Internal calibration
of the ADS1217 is called self calibration. This is handled with
three commands. One command does both offset and gain
calibration. There is also a gain calibration command and an
offset calibration command. Each calibration process takes
seven t
DATA
periods to complete. It takes 14 t
DATA
periods to
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADS1217IPFBT | 制造商:Texas Instruments 功能描述:A/D Converter (A-D) IC 制造商:Texas Instruments 功能描述:IC, ADC, 24BIT, 780SPS, TQFP-48 |
| ADS1217IPFBTG4 | 功能描述:模数转换器 - ADC 8-Ch 24-Bit ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADS1218 | 制造商:BB 制造商全称:BB 功能描述:8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER with FLASH Memory |
| ADS1218EVM | 功能描述:数据转换 IC 开发工具 ADS1218 Eval Mod RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| ADS1218Y | 制造商:TI 制造商全称:Texas Instruments 功能描述:8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER with FLASH Memory |
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