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参数资料
| 型号： | ADS1225IRGVT |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 24-Bit Analog-to-Digital Converter with One- and Two-Channel Differential Inputs and Internal Oscillator |
| 中文描述： | 24位模拟数字转换器与单和双通道差分输入和内部振荡器 |
| 文件页数： | 15/24页 |
| 文件大小： | 398K |
| 代理商： | ADS1225IRGVT |
www.ti.com
DATA RETRIEVAL
With the START pin high, the ADS1225 and
ADS1226 continuously convert the analog input
signal. To retrieve data, wait until DRDY/DOUT goes
low, as illustrated in
Figure 28
and
Table 5
. After this
occurs, begin shifting out the data by applying
SCLKs. Data is shifted out MSB first. It is not
required to shift out all 24 bits of data, but the data
must be retrieved before the new data is updated
(see t
2
) or else it will be overwritten.
DRDY/DOUT
23
22
21
1
24
0
LSB
MSB
Data
Data Ready
SCLK
START Tied High
t
DS
t
CONV
t
SCLK
t
SCLK
t
UP
New Data Ready
t
PD
t
HD
23
1
24
25
22
21
0
Data
25th SCLK to Force
/DOUT High
DRDY
Data Ready
New Data Ready
DRDY/DOUT
SCLK
ADS1225
ADS1226
SBAS346–MAY 2006
Avoid
DRDY/DOUT remain at the state of the last bit
shifted out until it is taken high (see t
6
), indicating
that new data is being updated. To avoid having
DRDY/DOUT remain in the state of the last bit, shift
a 25th SCLK to force DRDY/DOUT high (refer to
Figure 29
). This technique is useful when a host
controlling the ADS1225 and ADS1226 is polling
DRDY/DOUT to determine when data is ready.
data
retrieval
during
the
update
period.
Figure 28. Data Retrieval Timing
Table 5. Data Retrieval Times for
Figure 28
SYMBOL
t
DS
t
SCLK
t
PD
t
HD
t
UP
t
CONV
DESCRIPTION
DRDY/DOUT low to first SCLK rising edge
SCLK positive or negative pulse width
SCLK rising edge to new data bit valid: propagation delay
SCLK rising edge to old data bit valid: hold time
Data updating: no readback allowed
Conversion time (1/data rate), High-Speed mode
Conversion time (1/data rate), High-Resolution mode
MIN
0
100
MAX
UNITS
ns
ns
ns
ns
μ
s
ms
ms
50
0
29.5
8.0
45.5
49.2
13.3
83.3
Figure 29. Data Retrieval with DRDY/DOUT Forced High Afterwards
15
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PDF描述 |
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| ADS1225IRGVTG4 | 24-Bit Analog-to-Digital Converter with One- and Two-Channel Differential Inputs and Internal Oscillator |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADS1225IRGVT | 制造商:Texas Instruments 功能描述:A/D Converter (A-D) IC |
| ADS1225IRGVTG4 | 功能描述:模数转换器 - ADC 24-Bit 100SPS ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADS1226 | 制造商:AD 制造商全称:Analog Devices 功能描述:24-Bit Analog-to-Digital Converter with One- and Two-Channel Differential Inputs and Internal Oscillator |
| ADS1226IRGVR | 功能描述:模数转换器 - ADC 24-Bit ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADS1226IRGVRG4 | 功能描述:模数转换器 - ADC 24-Bit ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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