参数资料
型号: ADS5103CPFB
厂商: Texas Instruments, Inc.
英文描述: 1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE
中文描述: 1.8 - V模拟电源,10位,65/40 MSPS的模拟到数字的,具有内部参考变换器
文件页数: 7/23页
文件大小: 334K
代理商: ADS5103CPFB
ADS5102
ADS5103
SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001
15
www.ti.com
TYPICAL CHARACTERISTICS
Figure 27
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ADS5102
SFDR, SINAD
vs
CLOCK DUTY CYCLE
AVDD = DVDD = 1.8 V
DRVDD = 3.3 V
Fclk = 65 MHz
fi = 32.49 MHz at –1 dBFS
Clock Duty Cycle – %
SFDR,
SINAD
dBc
SINAD
SFDR
Figure 28
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30
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55
60
65
70
ADS5103
SFDR, SINAD
vs
CLOCK DUTY CYCLE
AVDD = DVDD = 1.8 V
DRVDD = 3.3 V
Fclk = 40 MHz
fi = 19.99 MHz at –1 dBFS
Clock Duty Cycle – %
SFDR,
SINAD
dBc
SINAD
SFDR
PRINCIPLES OF OPERATION
analog-to-digital converter
The ADS5102/3 is designed using a switched capacitor pipeline architecture fabricated in CMOS process. The
pipeline architecture is implemented with 10 stages, thus allowing for high conversion speed and exceptionally
low power. Each of these 10 stages produces one digital bit per stage. Both rising and falling edges of the clock
are used so the signal propagates thru the pipeline every half clock or five total clocks. Digital error correction
uses another 1/2 clock cycle at the end; thus the total pipeline latency is 5.5 clocks. (Refer to timing diagram
on page 7)
10-stage operation
The signal is sampled by the SHA. The first stage is digitized by 1.5 bits and sent to the digital error correction
block. This digitized value is then applied to a DAC, which recreates the analog value that has been digitized.
This value is then fed into a summing junction with the original input signal. The summing junction subtracts the
converted value from the original signal. This is known as the residue voltage. This residue voltage is then
amplified by a factor of 2x and transferred to the next stage. This is repeated for each of the 10 stages.
Each of the 10 pipeline stages, as well as the sample and hold amplifier, is differential in nature. This allows
rejection of any common mode signal. Thus a signal seen on Ain+ and Ain– is differentially seen as 0 V on the
output. This fully differential architecture allows higher ac performance of the ADC by reducing noise
susceptibility.
相关PDF资料
PDF描述
ADS5103CPFBR 1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE
ADS5103EVM 1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE
ADS5103IPFB 1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE
ADS5103IPFBR 1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE
ADS5413IPHP SINGLE 12-BIT, 65-MSPS IF SAMPLING ANALOG-TO-DIGITAL CONVERTER
相关代理商/技术参数
参数描述
ADS5103CPFBG4 功能描述:模数转换器 - ADC 10 Bit 40MSPS 1.8V Int/Ext Ref w/Pwrdwn RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
ADS5103CPFBR 功能描述:模数转换器 - ADC 10 Bit 40MSPS 1.8V Int/Ext Ref w/Pwrdwn RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
ADS5103CPFBRG4 功能描述:模数转换器 - ADC 10 Bit 40MSPS 1.8V Int/Ext Ref w/Pwrdwn RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
ADS5103EVM 功能描述:数据转换 IC 开发工具 ADS5103 Eval Mod RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V
ADS5103IPFB 功能描述:模数转换器 - ADC 10 Bit 40MSPS 1.8V Int/Ext Ref w/Pwrdwn RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32