参数资料
型号: ADS7825PG4
厂商: Texas Instruments
文件页数: 19/21页
文件大小: 0K
描述: IC MUX 16-BIT 4CH A/D 28-DIP
产品培训模块: Data Converter Basics
标准包装: 13
位数: 16
采样率(每秒): 40k
数据接口: 串行,并联
转换器数目: 1
功率耗散(最大): 50mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 28-DIP(0.300",7.62mm)
供应商设备封装: 28-PDIP
包装: 管件
输入数目和类型: 4 个单端,双极
7
ADS7825
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7825
Serial Output
±10V
+5V
0.1F 10F
+
NOTES: (1) DATACLK (pin 15) is an output when EXT/INT (pin 12) is LOW
and an input when EXT/INT is HIGH. (2) NC = no connection. (3) PAR/SER = 0V.
2.2F
+
2.2F
+
Convert Pulse
BUSY
SDATA
DATACLK(1)
EXT/INT
SYNC
R/C
40ns min
NC(2)
(3)
BASIC OPERATION
PARALLEL OUTPUT
Figure 1a shows a basic circuit to operate the ADS7825 with
parallel output (Channel 0 selected). Taking R/C (pin 22)
LOW for 40ns (12
s max) will initiate a conversion. BUSY
(pin 24) will go LOW and stay LOW until the conversion is
completed and the output register is updated. If BYTE (pin
21) is LOW, the 8 most significant bits will be valid when
pin 24 rises; if BYTE is HIGH, the 8 least significant bits
will be valid when BUSY rises. Data will be output in
Binary Two’s Complement format. BUSY going HIGH can
be used to latch the data. After the first byte has been read,
BYTE can be toggled allowing the remaining byte to be
read. All convert commands will be ignored while BUSY is
LOW.
The ADS7825 will begin tracking the input signal at the end
of the conversion. Allowing 25
s between convert com-
mands assures accurate acquisition of a new signal.
SERIAL OUTPUT
Figure 1b shows a basic circuit to operate the ADS7825 with
serial output (Channel 0 selected). Taking R/C (pin 22)
LOW for 40ns (12
s max) will initiate a conversion and
output valid data from the previous conversion on SDATA
(pin 16) synchronized to 16 clock pulses output on
DATACLK (pin 15). BUSY (pin 24) will go LOW and stay
LOW until the conversion is completed and the serial data
has been transmitted. Data will be output in Binary Two’s
Complement format, MSB first, and will be valid on both the
rising and falling edges of the data clock. BUSY going
HIGH can be used to latch the data. All convert commands
will be ignored while BUSY is LOW.
The ADS7825 will begin tracking the input signal at the end
of the conversion. Allowing 25
s between convert com-
mands assures accurate acquisition of a new signal.
(a)
FIGURE 1. Basic Connection Diagram, (a) Parallel Output, (b) Serial Output.
(b)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7825
Parallel Output
±10V
+5V
+5V(1)
0.1F 10F
+
D10
D9
D8
D2
D1
D0
D13 D12
D15
Pin 21
LOW
D14
D11
D5
D4
D7
Pin 21
HIGH
NOTE: (1) PAR/SER = 5V
D6
D3
2.2F
+
2.2F
+
Convert Pulse
BUSY
R/C
BYTE
40ns min
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